In terms of signal integrity, designers should attempt to follow a number of best practices (and answer a number of questions) when designing ICs and considering packages:
- Given use of a particular I/O cell, what is the power/ground pair-to-signal ratio that’s required based on the loads involved to achieve timing and signal-fidelity goals?
- How many I/Os can be switching at any given time and still achieve signal fidelity?
- How many power and ground pads are needed, and where should they be placed?
There are some generic rules of thumb when it comes to IC/package co-design. The most prevalent methods of interfacing IC die to package leadframes are wire bonds and flip-chip attachment. Because the power and ground interconnects with flip-chip attachment have inherently lower inductance, it generally makes for a more benign environment. Wire-bonded die require more thorough analysis.
The ratio of power/ground pairs to signal pads varies with speed, voltage levels, and various interface protocols. Designers must be careful about voltage domains, segregating them as best they can.
Placement of decoupling capacitors, or “decaps,” can be determined with a plot of impedances versus frequency. Such a plot will show where to place decaps to shift impedance peaks away from the frequency of operation, as well as dampen their amplitude. Designers tend to take on this task late in the IC-design process; earlier is better. An example of a tool that can create an impedance-versus-frequency plot is Rio Design Automation’s RioMagic.
