Ansys Adds Another Dimension to the 3D Chip Design Process

What you’ll learn:

• The advantages of 3D digital twins when it comes to building chiplet-based designs.
• The power-, heat-, and noise-related challenges that chiplets present to engineers.
• New capabilities of Ansys’s multiphysics software when connected to Omniverse.

Many of the world’s largest, most advanced chips can no longer fit on a monolithic slab of silicon. Instead, they comprise several smaller chiplets placed on 2.5D packaging studded with high-density interconnects or stacked in 3D configurations to mimic a system-on-chip (SoC). By binding these heterogeneous dies together in the package, designers can boost performance without increasing area or total power.

While 3D heterogeneous integration is a revolutionary step forward for chip design, it presents engineers with new challenges when it comes to managing the additional heat and reducing the electromagnetic interference (EMI) in the package.

Ansys is trying to solve these challenges by giving engineers more visibility into how all the components inside interact with each other. The company said it’s using NVIDIA’s Omniverse to create digital twins of 3D chips updated in real-time with results from its multiphysics software. A demo was recently on display at the Design Automation Conference (DAC), which covers the latest advances in silicon and system design.

“Traditional IC design can be seen as a top-down [2D] view of the world,” said Matt Commens, director of product management at Ansys. But, he added, as semiconductor companies start building out 3D chip designs, it becomes “a requirement to be able to analyze and diagnose in 3D.” In this case, Ansys is feeding information (electromagnetic fields and temperature maps, for instance) from its physics solvers into Omniverse, which overlays it on a virtual 3D version of the chip design.

Ansys is using NVIDIA’s Omniverse APIs to integrate the 3D environment into its physical simulation tools, including Icepak, Redhawk-SC, and HFSS. According to the company, this will allow engineers to zoom in and zoom out on different parts of a 3D chip design so that they can pinpoint hot spots or isolate unwanted sources of EMI. They can also use these digital twins to experiment with different arrangements of chiplets and examine what happens when other aspects of the architecture are changed.

Omniverse will give engineers the ability to design and simulate chiplets within the context of the larger processor, said Ansys, making it easier for them to optimize performance and diagnose potential issues.

The Future of Chips is All About Chiplets

As the semiconductor industry falls further behind Moore’s Law, chip designers are building the next generation of CPUs, GPUs, FPGAs, and even AI accelerators out of chiplets.

The scaling of transistors is becoming prohibitively costly, and the usual improvements in power, performance, and area (PPA) that come with every new process node are waning. Thus, semiconductor firms are pulling apart chips that are impractical or physically impossible to produce into several smaller building blocks that can be mixed and matched in a system in package (SiP). These chiplets are then bolted together with 2.5D or 3D packaging technologies—and sometimes both—that aren’t bound by the reticle limit of a single processor.

By spreading out a chip’s subsystems over several dies, chip designers can cram more square millimeters of silicon per package, squeezing in more transistors than possible in a single IC. Many of the most advanced 3D ICs integrate the latest logic technologies with memory and connectivity chiplets all within the same package, giving you more flexibility in optimizing PPA. Every die can be made using the process technology that suits it best, reducing complexity and costs.

The mixing and matching of heterogeneous dies—also called system technology co-optimization (STCO)—gives flexibility to companies racing to roll out domain-specific accelerators for AI, 5G, and other markets.

But building chips in three dimensions presents engineers with a wide range of power-, heat-, and noise-related difficulties. Unfortunately, 3D configurations of chiplets make tracing the origins of these problems a lot more challenging.

Thanks to the high density of transistors and the large amounts of current traveling between components, dissipating heat is no easy feat. When these silicon dies are stacked on top of each other, it becomes more difficult to remove the heat between them before it saps performance from the system. Also, transferring the heat out of one slab of silicon can negatively impact the thermal situation in other chips placed under or on top of it, adding to the complications.

The other threat is thermal expansion. As the temperature changes, different components in the package based on different nodes or different materials will expand at varying rates. These variations can physically strain the silicon dies, warping them in ways that impact overall performance and reliability. There are also larger thermal gradients in 2.5D and 3D packages since they squeeze in more silicon than a traditional chip in the same 2D area.

These chips are comprised of tens of billions of transistors linked through long interconnect wires weaving in and out of the silicon dies. Power is consumed when ferrying signals over long distances through these wires, creating additional heat that must be dissipated before it burns out the IC and diminishes performance. Everything pumping out heat in the device must be monitored to make sure that it can operate to the best of its ability.

Signal and power integrity are top priorities for any chip design. But supplying signals and power smoothly to all chiplets in 2.5D and 3D packages under dynamic loading conditions can be daunting due to their very complex geometries. What complicates this is the relationship between power and heat. The power used by each block in the system is different, which creates different heat distributions around every block.

Thus, these chips must be carefully designed to limit resistance and other parasitics, which are the bane of high-performance chips that have been the first movers to 2.5D and 3D packaging. They’re also exposed to EMI, which can disturb the smooth delivery of signals. High currents traveling between the silicon dies in the package can also increase the risk of electromigration, which could cause permanent damage over time.

As a result, Ansys and other industry giants are rolling out more advanced design and simulation software tools so that they make sense of the intricate geometry and material complexity lying within 3D packages.

The Power of Digital Twins for 3D Chip Design

Omniverse is adding another dimension to Ansys’s multiphysics software, which is widely used by chip engineers to solve heat, power, noise, and other problems that can take a toll on high-performance silicon.

Using Omniverse to upgrade Icepak, engineers are able to examine and simulate the heat distributed on the chip according to different power profiles and different arrangements of dies, as well as how heat is dissipated. Finding hot spots can help engineers optimize the layout of chiplets and make sure they’ve placed them in the right spot along with heatsinks or other cooling devices. Ansys said RedHawk-SC can be used to reduce voltage drop while ensuring the efficient and reliable delivery of appropriate power to the chiplets.

“You can’t always pinpoint problems in 2D,” noted Commens. “Some insights can only be found by diving into the 3D structure, which Omniverse gives you in a very powerful, GPU-powered platform.”

Besides heat, one other example is electromagnetic coupling, which causes unwanted EMI and noise that can affect the performance and reliability of 3D chips. Commens said that while signals traveling through chips may be interfering with each other, it can be tricky to detect the problem and determine what caused it. In this case, Ansys uses Omniverse to create a digital twin of the 3D chip design, enabling you to pinpoint the source of the coupling problem.

“3D chip design is so complex that engineers need something powerful that allows them to interact with it,” said Rich Goldman, head of strategic partnerships at Ansys. “They need to have high-power hardware to do this. Omniverse is a rich environment with a rich ecosystem that allows you to create huge scenarios,” which Goldman said will lead to designers gaining the ability “to simulate their 3D-IC within the context of the system it exists in, and eventually, creating digital twins of 3D-ICs in their platforms.”

One of the tradeoffs with multiphysics software is that it’s computationally intense. Though Omniverse is powered by NVIDIA’s data-center GPUs, Ansys said it’s separately upgrading RedHawk-SC to run on NVIDIA's Grace superchips, which unite a high-performance GPU and Arm-based CPU in a single server module.

Check out more of our coverage of DAC 2024. Also, read more articles in the TechXchange: Designing with Chiplets.