Many of the biggest names in the semiconductor industry are going all-in on chiplets, piling them into CPUs, GPUs, and AI accelerators before binding them together with 2.5D and 3D packaging in a way that mimics a single, large system-on-chip (SoC). And most of these companies are also betting on the Universal Chiplet Interconnect Express (UCIe) as the industry standard way these heterogeneous dies will communicate with each other in the future.
Many of the world’s largest semiconductor firms and even many startups and systems companies are pushing for a standard die-to-die interface because it could open the door to the mixing and matching of chiplets designed by different firms. By making it possible to buy commercial off-the-shelf IP in the form of chiplets, UCIe could give them new ways to optimize performance, power, and cost. The UCIe Consortium is trying to help usher in this open chiplet ecosystem by releasing the latest UCIe specification—UCIe 2.0.
Intel’s Debendra Das Sharma, the chairman of the UCIe Consortium, said UCIe 2.0 is all about making it easier to develop, test, and manage system-in-packages (SiPs) that contain chiplets from different vendors.
Importantly, it can handle hybrid bonding and other types of 3D packaging that stack silicon dies directly on top of each other to offer higher transistor and bandwidth density. UCIe 2.0 also features a standard system architecture for manageability that places a management fabric within each chiplet for testing, telemetry, and debugging. Testing these slabs of silicon can be tricky after plugging them into 2.5D packages with other chiplets or placing them in between chips in a 3D stack.
UCIe 2.0 debuted at FMS 2024, the annual memory and storage technology conference in Santa Clara, Calif., and it’s fully backwards compatible with the existing UCIe 1.1 and UCIe 1.0 standards.
UCIe in 3D: Higher Bandwidth, Better Power Efficiency
It’s heady times in the semiconductor business. The scaling of transistors is becoming prohibitively costly at every new process node. But chiplets are giving companies another path for pushing Moore’s Law into the future.
The adoption of chiplets has been driven by several motivations:
- Avoiding very large die sizes: Slicing a processor into several chiplets that can then be repackaged could increase yields, reducing the cost and complexity of designing chips on leading-edge process nodes.
- Promoting heterogeneous integration: Integrating logic, memory, connectivity, and other chiplets based on the best process technology gives companies more flexibility to optimize performance and cost.
- Speeding up development of domain-specific silicon: Mixing, matching, and even reusing different types of chiplets could help reduce costs and time-to-market for AI accelerators and other custom chips.
In theory, companies could build differentiated chiplets in-house and then surround them with off-the-shelf chiplets to help shrink both their costs and time-to-market. But in practice, most companies build these chiplets by themselves and for themselves due to a wide range of technical and business challenges. Furthermore, they’re binding them together using proprietary interconnects and protocols that have made it much more difficult to bring third-party chiplets into the fold.
Instead of being developed behind closed doors, UCIe is trying to become the industry’s standard approach to the problems facing a commercial chiplet ecosystem.
In most cases, chiplets are placed on colossal slabs of silicon called interposers, while very small solder bumps connect the chips to the package, which are several times larger than the “reticle limit” of modern chips. A wide range of 2.5D packaging technologies are on the market, including TSMC’s CoWoS—the gold standard for GPU and other AI chips in data centers. These chips, surrounded by high-bandwidth memory (HBM), can squeeze in more than a thousand square millimeters worth of silicon each.
When it was introduced in 2022, UCIe 1.0 was all about 2D and 2.5D packaging. But the latest UCIe-3D specification can handle the high-density interconnects in 3D ICs, which stack silicon dies on top of each other to keep everything even closer. In these cases, even smaller bumps of solder—called micro bumps—serve as the die-to-die interconnects. The smaller the “pitch” between these tiny beads of solder, the faster the connection. At the same time, silicon vias distribute power vertically to the chiplets on the upper floors.
Many of the world’s largest semiconductor firms and packaging companies are trying to close the distance between the chips even further to bring about higher bandwidth density and better power efficiency. While the current state-of-the-art in 2.5D packaging can handle bump pitches between 50 and 30 µm, UCIe-3D is designed to be used with bump pitches from 10 to 25 µm and as small as 1 µm in the future, said Das Sharma.
UCIe-3D can also handle hybrid bonding, a type of 3D stacking technology that uses copper interconnects or “pads” to bring the chips face to face, closing the distance between them even further. By reducing the pitch from 25 µm in 2.5D packaging to 5 µm in 3D stacking, semiconductor companies can amass 25X more wires in the same space, slinging signals up to 12 TB/s for every square millimeter of silicon, said Das Sharma.
The other advantage of UCIe-3D is the entire chiplet can be used for die-to-die connectivity instead of requiring real estate on the chiplet’s “shoreline” for the PHY that physically links the chiplet to others around it. By reducing the distance between all of the dies, UCIe-3D also reduces the parasitics present in the interconnects, which not only improves the performance but also reduces power and, therefore, heat, said Das Sharma.
UCIe 2.0: Taking on the Challenges of Chiplet Testing
One of the other difficulties with chiplets is testing and debugging them—both inside the package and out.
While UCIe 1.0 gives semiconductor companies several ways to test and troubleshoot the interconnect, UCIe 2.0 is trying to solve challenges that remain at both the chiplet and the package level, noted Das Sharma. After chips are manufactured, but before they’re placed in a package, they’re rigorously tested to sort out the good from the bad. While it’s standard practice to test them through the small bumps of solder placed under each chip, the approach is impractical when it comes to solder bumps smaller than 25 µm.
Debugging poses another challenge for chiplets since they’re not all accessible from the package’s pins. While all chiplets are rigorously tested before being assembled in the package, they may not function the same in the context of the package due to the large amounts of heat and EMI inside. At the same time, you want to be able to manage the firmware under the hood of the chiplet relatively easily, said Das Sharma.
UCIe 2.0 is bringing the UCIe DFx Architecture (UDA) to the table to serve as the gateway for companies to access the test, debug, and telemetry capabilities within each chiplet. It features a management fabric that can be accessed at any time in the lifecycle of the chiplet—when it’s being tested on the factory floor, after being co-packaged with several other chiplets, and even after the final product is embedded in a system.
Chiplets placed at the heart of the package or in between other silicon dies can use the UDA architecture to relay signals used for testing, telemetry, and debugging to other chiplets in the package that have access to the package’s external pins. By sending these signals through other chiplets—not unlike the sprinters in a relay race—the new UCIe standard gives you access to chiplets that were once inaccessible for testing or debugging.
UCIe 2.0 is also adding a standard system architecture for managing the chiplets inside the package, giving them the ability to connect to external interfaces, including SMBus, PCIe, and others. Such an architecture allows for off-package connectivity. The management fabric in every chiplet features a “management transport” protocol that’s used to communicate with other blocks of the chiplet as well as across chiplets in the package, said Das Sharma.
Boyd Phelps, senior vice president of Cadence's Silicon Solutions, said of all the improvements in UCIe 2.0, “these are the right steps toward making UCIe a truly universal standard for chiplet interconnect.”
Check out more of our FMS 2024 coverage. Also, read more articles in the TechXchange: Designing with Chiplets.
