What you’ll learn:
- Why efficient network-on-chip (NoC) solutions are hard to build.
- How artificial intelligence is helping to improve NoC configuration.
A network-on-chip (NoC) is central to today’s system-on-chip (SoC) solutions that often incorporate GPUs and artificial-intelligence (AI) accelerators with a memory and CPU complex. Most electronic design automation (EDA) designers rarely design their own NoC from scratch.
Arteris's FlexNoC is an EDA tool for generating NoC logic to connect components on a chip based on a designer’s specification. FlexNoC handles the details while the designer defines where the connections go and what functionality is required. FlexNoC supports hard and soft tiling and AI is used to enhance the interconnect.
The latest enhancement is FlexGen. FlexGen provides additional automation building atop FlexNoC using AI heuristics, which the designer can customize by specifying goals. It helps optimize latency and reduce wire length and overall area (see figure).
Results from using FlexGen will vary depending on the chip components and design, but in many cases, FlexGen has improved productivity by a factor of 10 while reducing wire length by more than 25%.
Designers would use FlexNoC in an iterative fashion to design, test, and deploy NoC configurations. Beforehand, a designer needed to test each configuration manually. FlexGen does this automatically while enhancing the basic layout using AI to meet various goals that the designer can specify. Thus, the developer is able to balance size, power, performance, and latency. Scripting can be used to develop topologies, and an auto-timing closure assist addresses one of the most challenging aspects of NoC design—timing closure.
