What you’ll learn:
- How MIPS supports functional safety with RISC-V.
- What functionality is provided by MIPS RISC-V P8700 core?
- Why designers are looking to vendors like MIPS for solutions rather than the core IP.
The rise of RISC-V has been rapid, but adoption within safety- and security-critical spaces requires implementations that can meet requirements like ISO 26262 and ASIL B/D. In the video above, I talk with Sameer Wasson, CEO at MIPS, about the company’s “very MIPSy core,” the P8700 RISC-V core (Fig. 1).
The P8700 supports the RISC-V RV64GC instruction set architecture (ISA). The out-of-order (OOO), non-blocking execution unit includes an 8-wide instruction fetch with a 4-wide decode unit and a 7-wide issue queue. The core design maintains multi-cluster support along with PDtrace hybrid debug support.
Six of the P8700s fit into a cluster, and the implementation can be replicated up to 64 times to support 768 execution threads (Fig. 2). The cores have a 48-bit physical address space.
The MIPS Coherence Manager and shared virtual memory (SVM) use an AMBA ACE interface to tie the RISC-V clusters and the I/O coherence unit (IOCU). The manager supports up to eight units, which usually translates to six RISC-V cores and two IOCUs. The IOCU ports are optimized for low latency.
On the functional-safety side, the P8700 includes a fault bus that can be tied to external fault-handling logic. Parity is supported on all address and data buses. It’s also applied to software visible registers like the interrupt controller, cluster power controller (CPC) blocks, and global configuration registers (GCRs). Tag and data arrays provide ECC support.
