Core Offers A Double Dip Of Security And Compression

Available as a block of intellectual property from iTop Corp., the PCISAAC (PCI secured and accelerated/compressed) processor combines a PCI interface, LZW (Lempel Ziv Welch) compression and decompression, and AES (advanced encryption standard) encryption/decryption. The functionality has been proven by implementing the logic in an FPGA fabric (Xilinx XC2VP20).

In the FPGA fabric, AES encryption can be done at 55 Mbytes/s. As part of an ASIC implementation, the maximum speed increases to 66 Mbytes/s. For LZW compression, the FPGA implementation can deliver 41 Mbytes/s with a compression ratio of 1.7 and 78 Mbytes/s with a compression ratio of 3.3. When implemented as part of an ASIC, the LZW speeds increase to 49 and 94 Mbytes/s, respectively. At such speeds, the operations are transparent to most system users, with no effect on system performance.

To speed the data through the chip, DMA controllers are implemented on the input and output ports. They automatically read and write the files, offloading security/acceleration tasks from the computer's operating system and CPU, which in turn frees up the CPU to handle other tasks. The compression engine can be used to pack more data on a disk by compressing and decompressing files on-the-fly, while the companion AES engine is able to secure the data with minimal impact on the data rate.

For licensing details, contact the company.