IC Design Is At An Important Transition

The current growth spurt in the semiconductor industry is fueled mainly by consumer wireless applications, as evidenced by the phenomenal popularity of cell phones, gaming machines, PDAs, and iPods. Electronics manufacturers are in a constant race to create wireless devices that are ever smaller with more features, such as video, standby and sleep modes, to conserve power.

Development of the complex ICs in these devices requires advanced design techniques and nanometer process geometries, standards that conventional design solutions are not equipped to handle. Large design teams and lengthy design cycles also are required to produce these designs, making development costs for wireless devices prohibitively expensive at nearly $30 million per design.

IC design will become even more complicated as geometries continue to shrink in accordance with Moore's Law. Not only do EDA vendors include at least one additional feature for each process node, but also "niche" tools that only solve certain issues in the flow add to the design mix. Users must learn and operate these point tools, requiring additional resources, and the individual tools must be integrated into the design flow.

In order to operate within this design environment, the EDA industry must abandon conventional manual, point-tool approaches to cut overall design costs, reduce the size of design teams and accelerate the design flow. An IC design era must begin in which two-engineer design teams can deliver 10M-gate designs in a matter of weeks.

Design for manufacturability (DFM) requirements must be addressed throughout the physical implementation flow, not through time-consuming, post-layout fixes that often introduce new errors and further delay delivery. The solution lies with EDA software that provides true automation, tight integration and scalability.

One answer to all of the problems associated with conventional implementation flows is automated chip creation, which can dramatically change the physical implementation portion of the flow.

The first impact of this new flow is that irrespective of the size of the design, it is only necessary to have one (or, at most, two) physical implementation engineers associated with the project. Apart from anything else, this means that overall design costs can be reduced by as much as 30% to 50% because remaining engineers are freed up to work on other projects.

More important, physical implementation is no longer a bottleneck because the implementation engineers can engage much earlier in the project. By the time the RTL is 95% complete, the time taken to generate a new full-chip implementation from the ground up has risen to only two days or less, irrespective of the size of the design.

The fast turnaround time provided by an automated chip creation methodology enables predictability and early feedback on achievable performance. This allows system designers to perform "what-if" explorations on function versus cost with regard to the physical implementation. Furthermore, it allows design teams to spend more time experimenting at the architectural stage of the design, and to take full advantage of modern electronic system level (ESL) design tools.

The fact that the turnaround time required for a physical implementation to address significant functionality changes in the RTL can be reduced by 50% to 90% also means that late-stage changes to the design requirements can be accommodated without delaying the project schedule. Following the final pass once the RTL is 100% complete, automated sign-off verification prior to tapeout can be performed in only two hours.

Finally, an automated chip creation flow can offer better performance in terms of timing, area, power consumption, and signal-integrity compared to conventional flows. This means that the cost of manufacturing can be significantly reduced.

Economics drove the reality of Moore's Law. For this to continue, return on investment (ROI) and profit margins must be maintained. Automated chip creation can help preserve these critical margins for design implementation and analysis. Hopefully, ESL and other logic verification methods can help decrease the cost of verification as well. Once all of these solutions come together, ICs will play an even more integral part in our daily lives.