Fig 1. Altera’s NIOS II Embedded Evaluation Kit is a platform for checking out the 32-bit NIOS II soft-core processor.
Fig 2. Microsemi’s SmartFusion Evaluation Kit has an FPGA with a hard-core Arm Cortex-M3.
FPGA projects have been trending toward software solutions for years. Soft-core processors typically have been part of the designs because there have been limited options for hard-core processors. Xilinx was alone with its older Virtex FPGAs with a pair of 32-bit PowerPC cores. These devices targeted high-end applications and didn’t include peripherals to the cores except soft controllers provided by the FPGA. As a result, each design was unique.
Dealing with soft-core processors was on par with using these hard cores since peripherals and the processor had to be programmed into the FPGA before software could be run. I have used tools like Altera’s NIOS II Embedded Evaluation Kit that made this job significantly easier (Fig. 1). I also tried out BeMicro’s low-cost USB stick, which could be programmed with a NIOS II core (see “Stick It With NIOS II” at electronicdesign.com).
This year is going to be much different for developers.
Hard-Core Arm FPGAs
Microsemi’s SmartFusion was the first FPGA with a hard-core Cortex-M3 processor (see “FPGA Combines Hard-Core Cortex-M3 And Analog Peripherals” at electronicdesign.com). It has a complete set of hard microprocessor-style peripherals such as timers and UARTs in addition to direct access to the FPGA fabric. It also has its own flash and RAM independent of the FPGA fabric.
These features make SmartFusion a pretty powerful microcontroller. Yet it also has a high-performance analog subsystem accessible by the Cortex-M3, putting the hard section of this FPGA on par with some of the best microcontrollers on the market. Mix in the FPGA support and you have one powerful system.
I tried out the SmartFusion Evaluation Kit (Fig. 2). It compares favorably to the NIOS II kits because I was able to start programming the processor immediately. The big difference is that the core and peripherals always operate in the same fashion. Likewise, there is no need to check out the core’s logic because it does not change if the FPGA is reprogrammed. Granted, the soft core is already debugged, but the ability to reconfigure anything on an FPGA opens the possibility of interfacing issues.
Dealing with the SmartFusion chip from a software perspective was as easy as using any of the microcontroller kits I have worked with lately. Of course, taking advantage of the FPGA fabric is what really makes this kind of chip powerful, and it still requires an understanding of this type of logic design.
Still, the architecture isolates the FPGA design issues, and the FPGA programming can come from another party. This approach actually isn’t much different than downloading firmware to a peripheral, a task software developers are already very familiar with.
SmartFusion gets a bit more competition this year. Xilinx’s Zynq-7000 EPP ups the computational ante with a pair of Cortex-A9 processors (see “FPGA Packs In Dual Cortex-A9 Micro” at electronicdesign.com). This is the minimum platform for mid-range to high-end smart phones and tablets. Altera’s Cyclone and Arria lines now support dual-core Cortex-A9s as well (see “Dual Core Cortex-A9 With ECC Finds FPGA Home” at electronicdesign.com).
SmartFusion is in a different league from the offerings from Xilinx and Altera, but I suspect the families will grow so there will be more overlap. This simply means developers are going to have lots of options including augmenting the hard-core processors with additional software cores in the FPGA fabric.
Hard cores have more advantages than just stability and standard software interfacing. They also are more power efficient. The FPGA fabric will often dominate the design equation, but the combined hard core/FPGA will make ASICs a less desirable choice for many applications.
The Arm hard-core processors are likely to dominate designs, but they aren’t alone. Intel’s E600C mates an Atom processor to an Altera FPGA on a multichip carrier (see “Configurable Platform Blends FPGA With Atom” at electronicdesign.com). The connection is via two x1 PCI Express links.
The ability to count on the compute hardware benefits third-party software developers, so expect some interesting middleware to emerge.
