FPGA Design Tool Brings More Modularity To FPGA Design
ISE allows partitions to be locked during layout
ISE allows partitions to be locked during layout
Xilinx's latest incarnation of its Integrated Synthesis Environment, ISE Design Suite 12, now brings features such as ‘intelligent’ clock-gating technology to its line of FPGAs as well as a new modularity allowing easier integration of IP (intellectual property) from a variety of sources. The clock-gating technology can reduce dynamic power consumption by as much as 30%. On the modularity side, ISE now supports AMBA 4 AXI4-complaint IP for plug-and-play designs.
Some of the key drivers behind the new development platform include the need to reduce power while increasing performance. The ISE Design Suite 12 is designed to maximize the capabilities of Xilinx's Virtex-6 and Spartan-6 FPGAs while improving overall design productivity.
The new clock-gating support automatically detects and optimizes transitions with fine-grain logic slice optimizations. The algorithms analyze designs to identify sequential elements that do not change downstream logic and interconnect when toggled. The system then generates local clock enables within individual logic slices so they automatically shut down during unnecessary activity without having to shut off an entire clock network. The approach uses slightly more logic but it does not alter the existing logic of the system.
Modular FPGA Design
Xilinx went with ARM's AMBA 4 AXI4 protocol to standardize its IP interconnect. This is not suprising given Xilinx's support for hardware ARM cores in addition to support for soft core ARM processors. It delivers plug-and-play design. The AMBA 4 AXI4 specification defines a range of interconnect interfaces with several different buses that are optimized by application class. Also, the AMBA 4 AXI4 specification has been optimized for use with FPGAs. Xilinx worked with ARM to define the AXI4, AXI4-Lite, and AXI4-Stream specifications.
Designers can also use ISE 12 to partition their designs. Blocks can be locked to preserve placement and routing. These features are included in the "PlanAhead™ interface. ISE Design Suite 12 also expands on domain-specific methodologies with a number of infrastructure changes that improve software run times and design performance across all domains.
Software embedded developers can now leverage the pre-configured variables and settings of ISim (integrated simulator) to accelerate design verification. There is a new configuration wizard for the MicroBlaze soft processor. It enables optimization of embedded processor designs for minimized area, maximum performance (DMIPs), maximum frequency, or operating system usage (i.e. Linux requires an MMU). The configuration wizard also abstracts functionality such as cache size, behavior, and capability including usage of BRAM or Distributed RAM, branch prediction, plus control for pipeline stages, exception handling, debug access, and memory management functionality.
