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Small-Form-Factor FPGA Destined for Low-Power Apps

March 12, 2025
Altera’s Agilex 3 FPGA, built for power-constrained applications, almost doubles the performance of the Cyclone V.

What you’ll learn:

  • How Agilex 3 enhances AI designs.
  • How Altera addresses AI, security, and longevity.
  • How 12.5-Gb/s transceivers help improve FPGA designs.

 

FPGAs can tackle a range of applications from compact, low-power solutions to massive FPGAs with lots of hard-core processors that augment the logic fabric. Altera’s Agilex 3 family is intended for cost-effective applications with a small footprint FPGA—it delivers almost twice the performance of the company’s Cyclone V family while reducing power requirements (see figure). The FPGAs are built using Altera’s Hyperflex architecture.

The family can target everything from video object recognition for autonomous vehicles to implementing functional safety in smart factories. The artificial-intelligence and machine-learning (AI/ML) support makes it possible for the chip to handle the application on-chip.

The Agilex 3 family incorporates a pair of Arm Cortex-A55 processors running at speeds up to 800 MHz. Other hard logic includes LPDDR4 memory interfaces, a PCI Express (PCIe) 3.0 x4 interface, and up to four 12.5-Gb/s SerDes. The latter supports a physical coding sublayer (PCS), forward-error-correction (FEC) support, and the ability to handle 4x 10-Gb/s Ethernet. There are up to 14 MIPI D-PHY v2.1 interfaces that run at 2.5 Gb/s per lane. Support for 1.25-Gb/s low-voltage differential signaling (LVDS) is also in the mix.

The FPGA fabric can include up to 135K logical elements (LEs) in a 12- × 12-mm variable-pitch BGA (VPVGA) package. The fabric, which runs at 345 MHz, incorporates DSP with AI Tensor blocks for AI/ML applications. The AI Tensor blocks can deliver up to 2.8 INT TOPS.

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The Agilex 3 family is supported by Altera’s Quartus Prime Software. It has features like the NIOS V soft-core processor as well as the Altera FPGA AI Suite with machine-learning capabilities.

Altera’s Secure Device Manager (SDM) has built-in encryption and authentication. The FPGAs support physical anti-tamper detection. The system incorporates SHA-384, ECDSA 256/384 authentication, AES-256, and a physically unclonable function (PUF) key. These features help mitigate side-channel attacks, SPDM attestation, along with other cryptographic services.

The Agilex 3 family supports lifecycles of more than 15 years.

About the Author

William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.

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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.  

I still get a hand on software and electronic hardware. Some of this can be found on our Kit Close-Up video series. You can also see me on many of our TechXchange Talk videos. I am interested in a range of projects from robotics to artificial intelligence. 

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