The Changing Face Of Non-Volatile Storage

Aug. 15, 2013
The Flash Memory Summit was host to a range of new technology. Find our about 3D Vertical Flash and more.

Download this article in .PDF format
This file type includes high resolution graphics and schematics.

The Flash Memory Summit was host to a range of new technology, from LSI’s SandForce flash memory controllers utilizing a multi-level low-density parity check (LDPC) to the Hybrid Memory Cube (see “Hybrid Memory Cube Shows New Direction For High Performance Storage” at electronicdesign.com). The need for storage is insatiable. Three additional technologies look to address the issue: Samsung’s 3D flash architecture, Crossbar’s resistive RAM, and Diablo Technologies’ TerraDIMM (see “Large-Scale Flash Moves Next To The Microprocessor” at electronicdesign.com).

3D Vertical Flash

Samsung’s 3D V-NAND flash architecture increases capacity by layering 24 cells on top of each other (see the figure). The technology improves reliability by a factor of two to 10 while delivering twice the write performance of conventional 10-nm-class floating-gate NAND flash memory.

Figure 1. Samsung’s 3D flash technology improves storage density by packing 24 layers of MLC storage cells on top of each other.

Samsung is delivering 128 Gbits in a single chip using V-NAND’s 3D charge trap flash (CTF). The CTF architecture temporarily stores an electric charge in a non-conductive layer composed of silicon nitride (SiN) instead of a more conventional floating gate like most NAND technologies. A floating gate has more interference between cells as smaller geometries bring cells closer together.

Samsung uses a special etching technology to create the multilayer system. It punches holes through from the highest to the lowest layer of the chip. This is very difficult, but Samsung can now deliver chips on a regular basis.

Related Articles

Resistive RAM Is Non-Volatile

Crossbar delivers non-volatile storage using a new resistive RAM (RRAM) technology that is compatible with existing CMOS technology. It beats NAND flash with performance increased by a factor of 20. It also cuts power requirements by a factor of 20. It has an efficient 4F2 cell layout as well. RRAM is comparable in performance and endurance with other non-volatile technologies like MRAM (see “Magnetic DRAM Arrives” at electronicdesign.com) and PCM (phase change memory), but with a lower power requirement.

Crossbar’s announcement was about the technology versus chip delivery. It should scale well and even supports 3D stacking, but MRAM and PCM have yet to make a dent in flash except in niche markets. All three could give NAND flash a lot more competition in the future.

DIMM Flash

Diablo Technologies takes advantage of conventional MLC NAND flash but packs it onto a standard dual-inline memory module (DIMM). The TerraDIMM also includes the company’s secret sauce in the form of a memory controller that handles the NAND flash and the DDR3 protocol. A system can have a single TerraDIMM or multiple TerraDIMMs, and that’s key to its performance edge. The TerraDIMM already has an edge by using the fastest interface to the processor, the memory controller. High-end processors sport multiple controllers, and multichip processor clusters share memory from all the controllers.

The TerraDIMM differs from Viking Technology’s non-volatile DRAM, the ArxCis-NV (see “The Fundamentals Of Flash Memory Storage” at electronicdesign.com). The ArxCis-NV mirrors conventional double-data-rate (DDR) memory in NAND flash between power cycles. The TerraDIMM works like conventional flash, so device drivers make this NAND look like a solid-state disk (SSD) to the operating system. The system can do more, but that requires operating-system changes. These changes may show up in the near future, offering interesting application advantages.

Processor improvements will have to take a backseat to storage this year. These technologies are significant advances, and they are just the tip of the non-volatile iceberg. We may have more and faster cores, but new storage architectures will change how storage is managed and utilized.

Download this article in .PDF format
This file type includes high resolution graphics and schematics.

About the Author

William Wong Blog | Senior Content Director

Bill Wong covers Digital, Embedded, Systems and Software topics at Electronic Design. He writes a number of columns, including Lab Bench and alt.embedded, plus Bill's Workbench hands-on column. Bill is a Georgia Tech alumni with a B.S in Electrical Engineering and a master's degree in computer science for Rutgers, The State University of New Jersey.

He has written a dozen books and was the first Director of PC Labs at PC Magazine. He has worked in the computer and publication industry for almost 40 years and has been with Electronic Design since 2000. He helps run the Mercer Science and Engineering Fair in Mercer County, NJ.

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!