This article is part of the TechXchange: RISC-V: The Instruction-Set Alternative.
What you’ll learn:
- Why Synopsys’ entry into the RISC-V field is significant.
- What RISC-V families are supported by Synopsys.
Synopsys just released its ARC-V family of RISC-V-based processors (see figure). Those familiar with the company will know about the ARC family of IP processor cores that target embedded applications. The two families are distinct, but they share a lot of technology and Synopsys design expertise. Both are RISC processors with different instruction sets. This means that many technology features, such as instruction pipelines and caching, will be very similar.
The ARC-V RMX Series is a 32-bit microcontroller platform. The ARC-V RHX is a 32-bit, real-time, multicore application processor while the ARC-V RPX is a 64-bit platform capable of running operating systems like Linux.
The 32-bit ARC-V RMX Series, which supports a 3- or 5-stage instruction pipeline, is aimed at microcontroller applications like the Arm Cortex-M space. The 32-bit platform has optional DSP instructions.
The IP is available with functional-safety (FuSa) hybrid support. It’s designed to support ASIL B and ASIL D safety levels as well as acceleration for ISO 26262 and ISO 21434 automotive cybersecurity qualifications. The ARC-V FS processor IP was developed using Synopsys’ ISO 9001-certified Quality Management System (QMS).
The ARC Processor Extension (APEX) technology is an advanced instruction set extension for RISC-V. RISC-V designs can support additional instructions and APEX is a way to streamline implementation of these custom instructions. Synopsys delivers custom compiler support for these instructions.
The ARC-V RHX Series is a 32-bit multicore solution that handles up to 16 cores and is more on par with something like a 32-bit Arm Cortex-R. It uses a 10-stage, dual-issue instruction pipeline. It supports hardware virtualization, caching, and RISC-V vector extensions (RVV). The cores can be combined with hardware accelerators like Synopsys.ai. The multicore systems target real-time applications.
The company isn’t necessarily targeting high-end smartphone or server solutions with the 64-bit ARC-V RPX Series application processor cores, but they do contain the functionality needed for high-performance, embedded applications. This includes virtualization for operating systems like Linux with user/supervisor security. The cores support multi-cluster cache coherency with AMBA-CHI interfaces.
Synopsys’s entry into the RISC-V market is significant not only for the breadth of offerings out of the gate, but also for the level of expertise it brings to the table because of its existing ARC cores. While ARC has been very successful and will remain the choice for many companies, RISC-V’s popularity and growing ecosystem is not to be ignored.
Supporting an IP core isn’t just about the design of the core itself, but all that goes around it as well, from cache design to network-on-chip (NoC) fabrics. The ability to mix and match hardware acceleration is key to creating new chip designs quickly and reliably, with long-term support being critical for most applications.
Read more articles in the TechXchange: RISC-V: The Instruction-Set Alternative.
