Interest Widens In Analog Mixed-Signal Tools

In the relentless march toward smaller, lighter, and better mobile wireless devices, the ever-increasing integration of analog and digital circuits has been essential. This trend toward tighter integration is evidenced by the shift in importance from microprocessor and memory designs—the domain of the PC—to an increased design focus on DSPs and analog circuits—the domain of communication systems. Numerous studies have marked this shift from primarily digital design to mixed-signal design. In fact, some predict that as much as 33% of IC design will contain a mixed-signal component by 2005 (FIG. 1).

Today's wireless designs must handle signal speeds ranging from synchronized low-speed analog signals to higher-speed digital control signals. More and more designs include RF modules as well. In addition, analog/mixed-signal (A/MS) chips now contain integrated analog blocks, such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), phase-locked loops (PLLs), memory subsystems, RF modules, and adaptive filters.

A LOOK AT TOOLS Today's digital design methodologies tend to follow a top-down approach. In contrast, many analog designs flow from the bottom up. They start at the block level and then work up to the system or chip level with SPICE as the common level of abstraction.

This is not to say that analog behavioral models for higher-level development don't exist. Consider Verilog-A/MS, a language created by the Accellera EDA standards organization (www.eda.org/verilog-ams). It allows engineers to describe and simulate analog and mixed-signal designs using a top-down design methodology, as well as the traditional bottom-up approach. It does so by maintaining one netlist, rather than breaking the design into separate analog and digital blocks.

The IEEE VHDL-A/MS standard provides analog and mixed-signal extensions to the VHDL language (www.vhdl.org/vi/analog). These extensions enhance VHDL, thereby enabling it to support the description and simulation of analog circuits and systems. Both the Verilog-A/MS and VHDL-A/MS languages have been gaining support in the analog design community. Extensive model libraries for analog circuits complement the two standards. These libraries help to promote A/MS design reuse.

Nevertheless, the adoption of A/MS simulation tools has been slow, notes Raminderpal Singh, Co-Chairman for the Virtual Socket Interface Alliance's (VSIA's) A/MS Development Working Group. "Designers typically are resistant to changes. And the use of behavioral languages (such as Verilog-A/MS) can be complex to a designer typically used to drawing devices one at a time."

Yet the acceptance of these hardware description language (HDL) standards has grown. This trend has made it possible to develop tools that allow the designer to simulate and verify the analog and digital portions of a circuit together and at a higher level of abstraction. Simulation applications give designers the ability to evaluate performance at the chip level in advance of individual block-level design. While these tools aren't perfect, they do offer the analog designer a significant advantage in meeting time-to-market, performance, and cost constraints.

System-on-a-chip (SoC) design companies have begun to transition from traditional analog-only tools to next-generation analog hardware description languages like Verilog-A/MS and VHDL-A/MS, observes Jue-Hsien Chern, VP and General Manager for the Deep Sub-Micron Division at Mentor Graphics (www.mentor.com). As he explains, although these HDL extension tools have been around for several years, designers have been slow to adopt them because of the steep learning curve required to learn these languages, as well as the high initial capital investment for the applications.

Mentor Graphics has addressed these concerns, plus others, in its recently announced version of ADVanced Mixed Signal (ADMS). This simulation and verification program supports both analog and RF subsystems in A/MS SoC design. While the ADMS SoC tool suite works best when coupled with other Mentor applications, it can be inserted into any design flow with minimal difficulties. For example, ADMS now integrates Mentor's Mach TA for fast SPICE circuit simulation, Eldo RF for modulated steady-state simulation, and a new full-chip transistor-level parasitic extraction tool called Calibre xRC. At the same time, ADMS is a language-neutral program that supports existing analog standards. It also interfaces to libraries of behavioral templates that can be used for common designs, like analog filters and PLLs .

Another popular automated tool suite is Cadence's (www.cadence.com) A/MS Designer. This mixed-signal simulation program provides netlisting from schematics, as well as debugging, editing, and simulation control. It also includes ties to physical layout. Based upon Verilog-A/MS, A/MS Designer supports Verilog, VHDL, Spectre (the Cadence Analog Circuit Simulator), and SPICE. It allows the designer to simulate and analyze large and complex mixed-signal designs.

Sequence Design, which specializes in tools for A/MS design, complements Cadence's A/MS Designer by providing a powerful inductance extraction tool. Called Columbus-RF, it allows users to extract accurate inductance, capacitance, and resistance data from their layout. This effectively enables them to more closely analyze the behavior of the circuit.

Not to be left out, Synopsys (www.synopsys.com) recently entered the A/MS world with the latest release of VCS Verilog simulator. VCS 6.2 supports the Verilog-A/MS language through a platform called VCS Direct A/MS. This platform enables mixed-signal simulation of Verilog-A/MS and SPICE using a combination of the VCS Verilog and circuit simulators. Antrim Design Systems (www.antrim.com), uses its OmniSim simulator to interface with Synopsys' VCS Direct A/MS.

CHALLENGES AHEAD One of the major challenges to reducing design cost is the use of A/MS and RF-A/MS intellectual-property (IP) content. The continuing growth of the wireless market, in both cell phones and WLAN devices, means that RF-A/MS reuse will become increasingly important. The VSIA has recently released a specification document for RF-A/MS. It's actively extending this work into new process technologies.

Another A/MS chip-development challenge is the need to design and verify performance between the various tools used to create mixed-signal designs. This was one of the primary motivations for Agilent's alliance with Cadence, notes Dave Whipple, Product Manager for EEsof (http://eesof.tm.agilent.com). "Agilent's Advanced Design System (ADS) was architected to integrate system, baseband, and RF tools." The RF Design Environment (RFDE) focuses on RFIC design and was created out of this alliance between Agilent and Cadence.

The trend in mixed-signal SoCs has been moving toward a very large-scale, integrated, single-chip solution. This approach is seen as the best way to optimize a system design. Indeed, this may be the case for certain applications, such as low-performance, narrower-band, limited communication links like Bluetooth. But it's not the norm.

Consider the communications market, observes Dave Robertson from Analog Devices, Inc. (www.analog.com). In that market, cellular handsets continue to be accomplished through a set of ICs that are optimized for a specific set of functions in the signal chain (RF, baseband processing, DSP, etc.). Robertson explains that ADI has been promoting the concept of "smart partitioning," whereby a system's integrated chips can be partitioned to achieve optimal performance, price, and power dissipation. On the basis of this approach, ADI has developed and built its Mixed Signal Front-end (MxFE) portfolio of products for the broadband communications market (FIG. 2).

The future of wireless systems lies in the joint development of both analog and digital subsystems, whether it's as one chip or an integrated collection of chips. Automated tools and a coherent design strategy will continue to play a major role in the success of A/MS designs.