Modular FPGA Architecture Spawns Multiple Silicon Optimizations

Though FPGA designers have tried to keep FPGAs as generic as possible, Xilinx feels it's time to craft FPGAs that are more in tune to specific market segments. To do this, its next-generation Virtex FPGAs use a highly modularized architecture called the application-specific modular block (ASMBL).

In the ASMBL architecture, the FPGA logic is structured into long, narrow stripes. Each stripe can be defined during the silicon manufacturing stage as either the standard configurable logic elements or a function-specific block that contains specialized elements to handle DSP operations, memory, high-speed I/O, mixed-signal functions, or some other generic yet application-optimized function (see the figure).

Xilinx calls these application-optimized areas application "domains." Devices in the new family will contain as many as 1 billion transistors on one chip. Thanks to the domain-specific support, they'll provide performance and logic density previously only achievable through custom-designed ASICs.

To achieve the density without becoming I/O-pad-limited, Xilinx will use flip-chip packaging with the I/O and power connections distributed across the surface of the chip. The ability to distribute power and ground connections across the chip's surface also addresses some of the noise and signal-integrity issues. Designers can use as many contacts as needed to get clean signals.

Xilinx is defining the initial domain-specific stripes it plans to cointegrate with the FPGA stripes. It will sample the initial devices in the first half of 2004.