DUC And Enhanced FEC Arrive At The FPGA Core

Feb. 1, 2004
As major analysts predicted, FPGAs are continuing to expand into traditional ASIC and DSP markets. To take advantage of this growth, Xilinx is now offering a digital-upconverter (DUC) LogicCore module along with enhanced forward-error-correction...

As major analysts predicted, FPGAs are continuing to expand into traditional ASIC and DSP markets. To take advantage of this growth, Xilinx is now offering a digital-upconverter (DUC) LogicCore module along with enhanced forward-error-correction (FEC) cores for digital communication-system design. This step extends the company's coverage from baseband-processing applications to signal generation for digital intermediate-frequency (IF) subsystems. Having these functions in one FPGA should give users greater flexibility in their wireless designs.

The new DUC core is included with the Xilinx ISE software. Multiple DUC cores can be added to a single FPGA, thereby increasing the level of integration. Typical targets for DUC cores include software-defined radios; digital transmitters; cable modems; BPSK, QPSK, and QAM modulators; spread-spectrum communication systems; and CDMA2000 and 3G base stations. Filter lengths for the DUC core are selectable between 4 and 1024 taps. Designers can define coefficient precision from 4 to 32 b. The DUC core has been designed for use with Xilinx's System Generator for DSP software platform systems.

As mentioned, the company also announced enhanced forward-error-correction cores. They include a Reed-Solomon core that supports ITU-T J.83 variable block length and multi-channel capability. An enhanced convolutional interleaver core also is ready. It supports selectable configurations on the fly. In addition, the CDMA2000/3GPP2 Turbo Convolutional Codec (TCC) solution—which was announced as a beta product in July 2003—is now available as a production solution. These cores are part of the company's DSP intellectual-property (IP) offerings, which are used extensively in wireless and wireline communication systems.

The DUC LogicCore module and enhanced FEC cores are all available now. The DUC core is included with the latest version of the Xilinx CORE Generator System. The Reed-Solomon, Interleaver, and TCC cores are available as separately licensed parameterized netlists. Full-system hardware-evaluation versions of the Reed-Solomon and Interleaver cores also are available. All of the cores support the latest Xilinx Virtex and Spartan Series FPGAs and ISE 6.1I design software.

Xilinx, Inc.2100 Logic Dr., San Jose, CA 95124-3400; (408) 559-7778, FAX: (408) 559-7114, www.xilinx.com.

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About the Author

John Blyler

John Blyler has more than 18 years of technical experience in systems engineering and program management. His systems engineering (hardware and software) background encompasses industrial (GenRad Corp, Wacker Siltronics, Westinghouse, Grumman and Rockwell Intern.), government R&D (DoD-China Lake) and university (Idaho State Univ, Portland State Univ, and Oregon State Univ) environments. John is currently the senior technology editor for Penton Media’s Wireless Systems Design (WSD) magazine. He is also the executive editor for the WSD Update e-Newsletter.

Mr. Blyler has co-authored an IEEE Press (1998) book on computer systems engineering entitled: ""What's Size Got To Do With It: Understanding Computer Systems."" Until just recently, he wrote a regular column for the IEEE I&M magazine. John continues to develop and teach web-based, graduate-level systems engineering courses on a part-time basis for Portland State University.

John holds a BS in Engineering Physics from Oregon State University (1982) and an MS in Electronic Engineering from California State University, Northridge (1991).

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