Configurable Logic Solutions Wed FPGA Flexibility With ASIC Efficiency

An ASIC's or FPGA's ability to meet an application's demands comes down to a complex tradeoff between performance, density, time-to-market, and cost. Yet Leopard Logic combines FPGA flexibility with ASIC efficiency to do just that. Its Gladiator configurable logic devices (CLDs) achieve two to four times the performance of FPGAs with a tenth of their unit cost. On top of that, the nonrecurring engineering cost is a tenth that of a full ASIC design.

These CLDs combine several predefined but configurable functions, like blocks of dual-port RAM, multiple phase-locked and delay-locked loops (PLLs/DLLs), and multiple multiplier-accumulators (MACs). They also feature a mask-programmable array of logic cells and multiple blocks of SRAM-based configurable logic cells. All of these logic functions are, in turn, surrounded by configurable I/O banks (see the figure). On-chip system speeds of up to 500 MHz will be possible thanks to dedicated high-performance memories and MACs, as well as mask-programmable logic.

The five initial devices offer complexities ranging from 1.6 million to 25.6 million system gates (about 200k to 2.3 million ASIC gates). The logic on the largest chip is split between 256k cells of mask-programmable elements and 16k SRAM-based programmable cells. The chip also will pack 256 18- by 18-bit MACs to support complex DSP operations, 16 PLL/DLL blocks for clock timing, and 256 blocks of dual-port RAM (36 kbits/block).

The HyperBlox MP mask-programmable block and the HyperBlox FP SRAM-based field-programmable blocks share a common logic-cell architecture. As a result, circuit designs can be implemented without regard as to whether they will be implemented in the mask or field-programmable portions of the chip (see Drill Deeper 7326 for an online schematic of the logic-cell architecture).

Once the design is captured, the software tools can help partition the logic to place the speed-critical portions of the circuit in the mask-programmable HyperBlox portion of the chip and the less speed-critical functions in the FPGA HyperBlox. The design methodology, which uses standard ASIC design flows and tools, is fully integrated with industry-standard RTL design tools. So, users can achieve rapid timing closure on a desktop computer.

The ToolBlox suite lets designers implement and validate their circuits just like FPGAs. The process produces a bitmap that's sent to Leopard Logic. Samples are delivered in less than four weeks. Bitstreams for the chips' field-configurable portion are loaded through a JTAG or serial memory interface.

The first chip, the CLD6400, squeezes in 6.4 million system gates (about 800k ASIC gates), 64 dual-port memory blocks, 64 18-bit MACs (32 GMACs/s total maximum throughput), 16 PLL/DLL clocks, and 472 configurable user I/O pads. In lots of 100,000 units, the CLD6400 will cost $95 each in early 2005. Nonrecurring engineering charges are about $50,000.

See associated figure