More About Soft Silicon: Its Architecture And Performance
The Soft Silicon chip from Cradle Technologies contains three compute blocks, each called a Processing Quad (PQ). Each PQ packs four 32-bit RISC processors and eight 32-bit DSP engines. They also include local memory: 32 kbytes of instruction memory/cache, 64 kbytes of data memory/cache, and a memory-transfer engine. The RISC processors include both integer and IEEE 754 floating-point instructions. The 32-bit DSP engines incorporate 8-, 16-, and 32-bit fixed and floating-point instructions. A packed-in multiplier-accumulator can perform 16 8-bit operations or four 16-bit operations, or three floating-point operations every clock cycle.
The chip’s dual-channel I/O quad provides completely configurable I/O (PCI, 1394, Ethernet, SCSI, and other complex interfaces). It has two RISC processors, four memory-transfer engines, and an internal bus interface unit. The RISC engines in the I/O quad typically execute low-level drivers.
Each quad block ties into two high-speed local buses, one for data and one for instructions, that each provide 1.8 Gbytes/s of bandwidth for data movement. This is plenty of bandwidth for data movement between the on-chip blocks.
