Multistandard Wireless Accelerator Enables Emerging Basestation Technologies
A famous cartoon coyote once called Apetitius Giganticus wanted to catch a roadrunner that sometimes went by Accelerati Incredibilus. The coyote always used some outdated technology to try to catch the roadrunner, who relied on speed and simplicity to avoid becoming lunch. So if FPGAs and ASICs are the coyote and Freescale’s MSBA8100 wireless basestation accelerator is the roadrunner, then, well, you get the picture (Fig. 1).
The MSBA8100 is the very first wireless accelerator to support Third Generation Long Term Evolution (3G-LTE), along with the Worldwide Interoperability for Microwave Access (WiMAX), Evolved High Speed Packet Access (HSPA+), and Time Division Duplex LTE (TDD-LTE) protocols. If you’re in the business of manufacturing wireless infrastructure equipment, it can help lower costs and future-proof your system while still supporting legacy 2G/3G standards.
And by eliminating the need to both develop and buy an expensive FPGA or ASIC with the equivalent capabilities, you’ll keep that pesky coyote at bay. The device is typically used in conjunction with Freescale’s MSC8144 quad-core DSP, which is an established solution for a variety of basestation designs. Put it all together and you have a wireless basestation solution that handles data rates over 100 Mbits/s, provides low-latency packet I/O, and yet is practically cheap enough to purchase with leftover bird feed.
The MSBA8100’s Multi Accelerator Platform Engine for Baseband (MAPLE-B) block handles Fourier transforms, algorithm acceleration, and Turbo/Viterbi decoding (Fig. 2). The Fourier transform calculation engine can handle a variable number of points up to 200 Msamples/s (FFT/IFFT) and 130 Msamples/s (DFT/IDFT). The Turbo decoder can handle up to 150 Mbits/s and the Viterbi decoder can handle 85 Mbits/s, and each supports various standards.
The device also includes an internal 512-kbyte low-latency M2 memory. Its double-data rate (DDR) SDRAM controller supports both DDR and DDR2 at up to 333 MHz for devices up to 4 Gbits (x8 and x16). For inter-device communications, the MSBA8100 provides two Serial RapidIO (SRIO) 1.2 ports and a PCI port. Each SRIO port supports up to four lanes operating at up to 3.125 Gbaud, and the SRIO blocks include a RapidIO messaging unit (RMU) and a RapidIO DMA unit. The 32-bit PCI 2.2 port can operate at 33 and 66 MHz.
Tying everything together and policing the device, a chip-level arbitration and switching system (CLASS) arbitrates the MAPLE-B bus, the SRIO controllers, the internal memory interface, the DDR SDRAM controller, the PCI target, and the device configuration control and status registers. Two configurable RISC engines can handle any required updates just in case Mr. Giganticus devises some new plan to thwart poor Mr. Incredibilus. The MSBA8100 devices should be sampling sometime this quarter.
Freescale Semiconductor