32-Bit DSC Architecture Fits Ultra-Low-Power Applications
The Cortex-M4, the latest in ARM’s Cortex line of microcontroller architectures, extends the 16/32-bit instruction set of the popular Cortex-M3 architecture that is in turn a superset of the Cortex-M0 and Cortex-M1 architectures. It targets digital signal controller (DSC) applications and can include an optional floating-point unit (FPU).
Based on the ARMv7ME architecture that implements the Thumb-2 instruction set, the Cortex-M4 adds DSP and single-instruction multiple-data (SIMD) extensions that are implemented using a single-cycle 32-bit media access controller (MAC) with a 64-bit accumulator. The additional floating-point instructions are designated Cortex-M4F. The FPU implements IEEE single precision support.
Based on a three-stage pipeline with branch speculation, the Cortex-M4’s microarchitecture is designed to run at 150 MHz. Three AHB-LiteBus interfaces connect peripherals. The interrupt controller is compatible with the Cortex-M3 and handles up to 240 interrupts and priorities. The memory protection unit (MPU) and debug and trace are optional. The standard configuration requires 65 kgates. The FPU adds 25 kgates to the total.
The system is designed for ultra-low-power environments with features like a deep-sleep mode and wakeup interrupt support. The core is designed to require less than 40 µW/MHz. A typical application such as an MP3 decode consumes only 0.5 mW. The FPU also can be powered down to conserve energy.
The architecture follows the Cortex Microcontroller Software Interface Standard (CMSIS) and provides CMSIS-Expanded with Cortex-M4 features for the additions to the architecture family. CMSIS-compliant C Compilers support the Cortex-M4 extensions.
The Cortex-M4 can attack new application areas for ARM and its customers. It will make the architecture more amenable to single-chip solutions where DSPs or DSCs were sometimes paired with ARM processors to gain software flexibility while providing higher performance. The Cortex-M4 offers the flexibility and power in a single chip. The architecture will be used in custom chips and will likely show up in standard microcontrollers soon.
