Zynq-7000 EPP architecture
Zynq-7000 EPP specifications
Xilinx's transition from Power to Arm cores is complete but the latest Zynq-7000 EPP (Extensible Processing Platform) is much more than just adding a pair of hard cores to an FPGA. The Zynq-7000 EPP architecture (Fig. 1) is more of a multicore microcontroller with an FPGA rather than and an FPGA with some hard cores. This is highlighted by Xilinx's family of Zynq-7000 EPP chips (Fig. 2). All four of the EPP FPGAs has the same dual core microcontroller. They differ in the size of the FPGA and the number of FPGA-related interfaces and logic such as DSP blocks, PCI Express interfaces and high speed SERDES.
Xilinx's approach is not unique. Intel and Altera teamed up to create the E600C Atom (see Configurable Platform Blends FPGA With Atom) the includes 40nm Arria II FPGA. Altera also has hard Arm cores in its plans as well.
The bigger question is whether this trend towards micro-centric configurable platforms will dominate FPGA use. I suspect that will be the case. Soft cores were already dominating new FPGA projects. Hard cores are often more efficient. They are also easier to work with.
So what is in the Zynq-7000's microcontroller? It starts with a pair of 800 MHz Cortex-A9 MPcores that includes NEON SIMD support in addition to a double precision floating point unit. The rest of the processing engine is relatively common with 32 Kbyte instruction and data caches and a 512 Kbyte L2 cache.
The chips have 256 Kbytes of RAM. It also has memory controllers for off-chip memory. These include support for DDR2/3, LPDDR2, QSPI, NOR, and NAND flash. The system supports secure booting even from QSPI devices. The processor can load the FPGA configuration. A common AXI-4 interface provides a link to the FPGA. Xilinx and third party IP are designed to work with the AXI-4 interface.
Analog support is not extensive but it does have a 16-channel, dual 12-bit ADCs that can handle 1 Msample/s. The ADC also has access to on-chip sensors. It can also be controlled by the FPGA logic.
There are 8 DMA channels that support the ADC and other communication peripherals. These include a pair of USB 2.0 OTG interface and two tri-mode Gigabit Ethernet interfaces. There is also two SD/SDIO, UART, CAN, I2C, and SPI interfaces.
That sounds like a typical high performance multicore microcontroller, which it is. Power management is on par with other platforms. Performance is managed on a per core basis. The FPGA supports clock gating but it cannot be powered down like the microcontroller or some of its peripherals.
Xilinx is supporting the family with its Eclipse-based development environment in the Xilinx Platform Studio Software Development Kit (SDK). The microcontroller is also supported by the ARM Development Studio 5 (DS-5) and the ARM RealView Development Suite (RVDS). FPGA development is supported by Xilinx's ISE Design.
The Zynq-7000 family is designed to address a range of applications. The low end Z-7010 could handle driver assistance chores or multifunction printers. The Z-7020 can do this as well LTE applications. The Z-7030 and Z-7040 add high speed serial interfaces that can provide access PCI Express peripherals. These are ideal for high end routers. All are going to find a home in avionic and military environments.
