64-bit MIPS Architecture Targets High Performance Designs
Imagination Technologies latest 64-bit processor architecture targets high performance mobile applications. The Warrior Class I6400 (see the figure) is Imagination’s mid-range offering. It supports simultaneous multithreading (SMT) that allow the system to execute multiple instructions from multiple threads. Each core can run four threads. A quad core system can fit on 1 mm by 1 mm space running at over 1 GHz.
The system uses a new directory-based coherent cache manager. Other system typically use a snooping approach. The L1 cache is mirrored in L2 allowing more system flexibility since all cores can operate independently including operating at different speeds. ECC is used with all caches. Hardware prefetch reduces memory latency overhead.
The core is designed to be used in coherent clusters with up to six cores. The architecture supports 64 clusters for a total of 1536 threads. The design supports AXI4/ACE system interfaces.
The I6400 runs 32-bit and 64-bit instruction sets. The 64-bit instruction set is a proper superset of the 32-bit version so there is no mode switch necessary. The additional instructions support 64-bit data types along longer relative referencing.
The system includes a 128-bit SIMD unit. The RISC-based unit has a symmetrical, orthogonal design. The instruction set is independent of register width and they support compare and branch instructions. It has 32 128-bit registers. The architecture is designed to support high level parallel programming platforms like OpenCL.
Hardware virtualization support includes virtualized interrupt controller support as well as I/O virtualization.
The PowerGearing power management provides fine grained, block- and core-level clock gating. Each core in the cluster is independently controlled including the ability to sleep. Dynamic voltage and frequency scaling is supported.
