This article is part of the TechXchange: RISC-V: The Instruction-Set Alternative.
The 2024 RISC-V Summit is already in the planning stages, but if you missed attending the 2023 version, then you're in luck. The keynote and technical session videos are available.
I was able to attend but missed most of the technical sessions. I picked a few of my favorites and included them below. The first is a long one by Keith Graham from Codasip on custom instructions for RISC-V. Like Arm and other embedded processor architectures, the RISC-V instruction set doesn't define all combinations.
Normally, invalid instructions trap, but it's possible to utilize those to do something useful. In this case, the processor design is augmented and the matching compiler can take advantage of these new instructions to implement code to run faster or more efficiently. Of course, doing this isn't necessarily as easy as it sounds.
The next session is about accelerating artificial-intelligence (AI) applications on the edge. This is a relatively short session by Florian Zaruba from Axelera AI. The company specializes in multimedia processing using AI models.
The last one in my selection focuses on compiler optimization, particularly LLVM. SiFive's Ivan Baev talks about making LLVM more performant.
That's it for now. Leave a comment about what session you liked most. That kind of feedback is very useful when writing more in-depth articles. You can also answer the quick poll below. Check out other Quick Polls on Electronic Design.
