Imperas Software, a developer of RISC-V processor verification technology, announced as part of the participation at DVCon 2021, Simon Davidmann will host a personal perspective on the formation and history of SystemVerilog with the co-founders of Verilog and SystemVerilog. In 1997, Co-Design Automation Inc., was set-up by Simon Davidmann and Peter Flake, to design and implement a new language and simulator. Phil Moorby joined in 1999. The company name showed the desire to include software/hardware co-design, but there was more customer interest in hardware design and verification, and even system specification.
Their original vision of Superlog (derived from Super and Verilog) was to have a single language for system specification, hardware design, hardware verification, and software development. Superlog was later renamed to SystemVerilog as it became adopted by Accellera and later became an IEEE standard. In 2020, Peter Flake, Phil Moorby and Simon Davidmann reunited to collaborate on a paper (with Arturo Salz and Steve Golson) charting the history and development of Verilog, Superlog and SystemVerilog which is to be presented virtually at the ACM (Association for Computing Machinery) prestigious HOPL IV event in 2021 which is held every 10 years. The full text of the paper, ‘Verilog HDL and Its Ancestors and Descendants’, is available at https://dl.acm.org/doi/10.1145/3386337.
Imperas will host ‘A personal perspective on the history of SystemVerilog / Superlog’ together with guest speakers:
Phil Moorby, inventor of Verilog HDL and Verilog-XL simulator
Peter Flake, inventor of HILO and Superlog, SystemVerilog
Simon Davidmann, HILO, Superlog, SystemVerilog
When: Tuesday March 2nd at 4pm PST
Philip Moorby, Inventor of Verilog HDL. Inventor of Verilog-XL simulator. In 2005 received the Phil Kaufman Award [Aycinena 2005; EDAC 2005; Goering 2005; Newton 2005] presented by the EDA Consortium (now the ESD Alliance) for creating and helping to popularize the Verilog Hardware Description Language. In 2016 received a Fellow Award [CHM 2015, 2016] from the Computer History Museum: For his invention and promotion of the Verilog hardware description language.
Peter Flake, Researcher at Bradford University, then Brunel University, Technical Manager at Cirrus Computers, then Director of Technology at GenRad. Architect at Cadence, Chief Technical Officer at Co-Design Automation, Scientist at Synopsys. Worked on all HILO projects, Superlog and SystemVerilog.
Simon Davidmann was Involved in the Verilog evolution from HILO to SystemVerilog. Worked on HILO 2 as a Fellow at Brunel University and at Cirrus. As application manager at Cirrus-USA supported early HILO customers including Gateway founders, Prabhu Goel and Chi-lai Huang, at Wang Labs. Drove European adoption of Verilog as Technical Manager at Gateway and later promoting VCS as European VP at Chronologic Simulation. Founder and CEO of Co-Design. Drove standardization of SystemVerilog as VP at Synopsys. Founder and CEO of Imperas.