Imperas Software, a creator of virtual platforms and high-performance software simulation, released the riscvOVPsimCOREV as a free ISS (Instruction Set Simulator) based on the Imperas reference models of the OpenHW Groups processor RISC-V core IP. An ISS is the essential starting point for software development tasks of algorithm, application, and tool writing. riscvOVPsimCOREV can be configured for the complete range of the OpenHW CORE-V processor IP portfolio, including the RTL-frozen CV32E40P (formally known as PULP RI5CY), the under-development CV32E40S and CV32E40X, plus the upcoming CVA6-32/64 bit (formally known as PULP ARIANE), and will be extended overtime to cover the future roadmap of CORE-V.
An ISS is a software based representation of a processor that can be used to test and develop software on a standard host x86 PC machine. The main advantages of an ISS over a traditional hardware development platform are the ease-of-use features that help the programmer with debug, control and visibility of code running in simulation. With new processor IP cores, the ISS is an essential tool to support the development of software before silicon or hardware implementations are available. Many developers rely on a broad set of tools for software development that are packaged as an IDE (Integrated Development Environment).
Typically, an IDE includes utilities and supporting technologies such as compiler, debugger, ISS, and other productivity tools. To support integration with IDE’s and other software design methodologies such as CI/CD (Continuous Integration and Continuous Deployment) platforms, riscvOVPsimCOREV features configuration and interface options such as debug port and trace to allow easy integration.
riscvOVPsimCOREV is a free RISC-V reference model and simulator (ISS) that includes a proprietary freeware license from Imperas, which covers free commercial as well as academic use. The simulator package also includes a complete open-source model licensed under the Apache 2.0 license, and is available for download now at https://github.com/openhwgroup/riscv-ovpsim-corev. riscvOVPsimCOREV is licensed as closed source freeware, a common approach to software licensing which allows distribution without monetary cost to the end user.
OpenHW Day - April 1st 2021
Imperas will present several technical talks including demonstrations with riscvOVPsimCOREV at the OpenHW Day on April 1st 2021, which is part of the 3rd annual RISC-V Week. For additional information and free registration please visit https://open-src-soc.org.