Two separate partnerships between Synopsys and intellectual-property (IP) providers hope to speed the adoption of the high-speed PCI Express architecture. In teaming with Rambus Inc. and Artisan Components Inc., Synopsys hopes to demonstrate the interoperability of each vendor's PCI physical-layer (PHY) IP in a low-risk implementation environment.
Synopsys will pair its DesignWare PCI Express endpoint controller core with Rambus' RaSer PHY core for a demonstration at this year's PCI Express Interoperability Workshop. The platform demo will consist of two boards: a motherboard built by Synopsys that uses FPGAs to house the endpoint controller core with driver software, and a daughterboard consisting of Rambus' PHY IP.
The interface between the two will adhere to the PHY Interface for PCI Express (PIPE) specifications. On the motherboard will be three critical protocol layers (the logical PHY layer, the data-link layer, and the transaction layer), while the daughterboard will include the analog physical media attachment sublayer and the physical coding sublayer.
Synopsys' collaboration with Artisan Components will yield a similar demonstration at the Interoperability Workshop. Again, Synopsys' endpoint controller core will be paired with Artisan's PCI Express PHY IP to show that the resulting implementation represents a low integration risk for system developers. The Artisan daughterboard will contain a complete serial link, including multiplexer/demultiplexer, 8b/10b encode/decode, elastic buffer, and clock-recovery circuitry that's compatible with the PCI Express Base 1.0a specification.
For more information, visit www.designware.com, www.rambus.com and www.artisan.com.
