Power-Management ICs Are Ideal For DDR-SDRAM Memories

Double-data-rate, single-data random access memory (DDR-SDRAM) has become popular in desktop and portable computing. The reason is its superior performance, low power dissipation, and competitive cost compared to other memory technologies.¹

DDR initially had a 266-Mbyte/s data rate versus a 133-Mbyte/s data rate for plain SDRAM. Subsequently, the DDR data rate has increased to 400 Mbytes/s. A second-generation DDR, or DDR2, debuted at the beginning of 2004. This extended the data rate from 400 up to 667 Mbytes/s, while reducing power consumption further.²

First-generation DDR still dominates the market, but DDR2 is gaining market share fast. Additionally, a transition crossover is expected by the end of 2005. But no matter the flavor, DDRx memories require a new and more complex power-management architecture compared to the previous SDRAM technology.

DDR POWER-MANAGEMENT ARCHITECTUREFigure 1 illustrates the basic power-management architecture for first-generation DDR memories. In DDR memories, the output buffer is a push-pull stage, while the input receiver is a differential stage. This requires a reference bias midpoint, V_REF, and consequently, an input voltage termination that can source, as well as sink, current.

This last feature (sourcing and sinking current) differentiates the DDR V_TT termination from other terminations present in the PC motherboard. This difference is especially noticeable in the termination for the front system bus (FSB) that connects the CPU to the memory channel hub (MCH), which requires only sink capability due to termination to the positive rail. Hence, such DDR V_TT terminations can't reuse or adapt previous V_TT termination architectures, and they require a new power design.

The logic gates in first-generation DDR memories are powered from 2.5 V. Be-tween any output buffer from the chip set and the corresponding input receiver on the memory module, we typically find a routing trace or stub that needs to be properly terminated with resistors RT and RS (Fig. 1, again). When all impedances (including that of the output buffer) are accounted for, each terminated line can sink or source ±16.2 mA.³ For systems with longer trace lengths between transmitter and receiver, it may be necessary to terminate the line at both ends, doubling the current.

The 2.5-V V_DDQ required for the DDR logic has a tolerance of +200 mV. To maintain noise margins, V_TT must track V_DDQ. It has to equal V_DDQ/2, or approximately 1.25 V, with an accuracy of ±3%. Finally, V_REF must equal V_TT to +40 mV. These tracking requirements, plus the requirement that V_TT can both sink and source current, present unique challenges in powering DDR memory.

WORSE-CASE CURRENT CONSUMPTION —VTT Termination: Assuming the following structure for a 128-Mbyte memory system:

128-bit wide bus
8 data strobes
8 mask bits
8 V_CC bits
40 address lines (2 copies of 20 addresses)

192 lines

With each line consuming 16.2 mA, we have a maximum current consumption of:

192 × 16.2 mA = 3.11 A peak-V_DDQ Power Supply: V_DDQ sources current during the phase in which V_TT sinks current. It follows that the current for V_DDQ is unipolar, and its maximum equals the maximum value required of V_TT, 3.11 A.

Average Power Consumption: A 128-Mbyte memory system typically comprises 8- by 128-Mbit devices and consumes an average power of 990 mW, excluding the V_TT termination power.⁴ It follows that the average current I_DDQ drawn from V_DDQ will be:

I_DDQ = P_DDQ/V_DDQ = 990 mW/2.5 V = 0.396 A

Similarly, the average power consumed by the termination resistors, P_TT, is 660 mW.¹

It follows that I_TT, the current drawn from V_TT, will be:

I_TT = P_TT/V_TT = 660 mW/1.25 V = 0.528 A

Finally, the V_REF current (I_REF) is selected to be high enough for the V_REF supply to exhibit low enough impedance to yield good noise immunity (less than 5 mA).

In summary, the main static parameters for the design of a 128-Mbyte DDR memory power-management system are:

V_DDQ = 2.5 V, I_DDQ = 0.396 A average, 3.11 A peak (source)

V_TT = V_DDQ/2 = 1.25 V, I_TT = 0.528 A average, 3.11 A peak (source and sink)

V_REF = V_DDQ/2 = 1.25 V, I_REF = 5 mA

Naturally, if V_DDQ is used to power other loads besides the termination load, its sizing must be increased accordingly.

TRANSIENT OPERATION The governing documents for DDR memory, JEDEC JESD79 and JESD 8-9, specify that the V_TT voltage must equal half of the V_DDQ voltage with a tolerance of ±3%. This tolerance should include load transients on the bus caused by the lines transitioning. However, two items necessary to evaluate the capacitor requirements for the V_TT supply are missing. The JEDEC spec doesn't say with what bandwidth V_TT must track V_DDQ, nor does it specify V_TT's maximum load transient.

In practice, it appears that the spec is intended to maximize noise margins. So while it's not mandatory for V_TT to follow half of V_DDQ at all times, the greater the bandwidth with which it does so, the more robust the system. Consequently, a wide-bandwidth switching converter is desirable for generating V_TT.

For the V_TT load transient, the current conceivably could step from +3.11 A down to ±3.11 A, from sourcing to sinking current. This 6.22-A step with a 40-mV window would require an output capacitor with an effective series resistance (ESR) of only 7 mW. Two practical considerations moderate this requirement, though. First, actual DDR memory doesn't really draw 3.11 A. Measurement shows typical current in the range of 0.5 to 1 A. Second, the transition between sinking and sourcing current occurs very quickly, so quickly that the converter doesn't see it. To go from positive maximum current to negative maximum current would require that the bus go from all ones to all zeros and then remain in that state for a time at least equal to the inverse of the converter bandwidth. Because this is on the order of 10µs, and the bus runs at 100 MHz, it would need to stay at all zeros for 1000 cycles! In practice, then, the output capacitor for V_TT need be only about 40 mW ESR.STANDBY OPERATION DDR memory supports standby operation. In this mode, the memory retains its contents but is not actively addressed. Such a state may be seen, for example, in a notebook computer in standby mode. The memory chips aren't communicating in standby, so the V_TT bus power can be turned off to save power. V_DDQ, of course, must remain on for the memory to retain its contents. LINEAR VERSUS SWITCHING As noted earlier, the average power dissipation of a DDR system is:

P_DDQ = 990 mW

P_TT = 660 mW

for a total of P_TOTDDR = 990 mW + 660 mW = 1650 mW. In comparison, a comparable SRAM system consumes 2040 mW.⁴

If a linear regulator were used to terminate V_TT, the P_TT power would be processed with 50% efficiency according to the ratio V_OUT/V_IN = V_TT /V_DDQ = 0.5. So an additional 660 mW of power is dissipated in the V_TT regulator, raising the total average power dissipation to 1650 + 660 = 2310 mW. Such a figure now exceeds the corresponding power-dissipation figure for SDRAM, wiping out one of the advantages of the DDR memories—namely lower power dissipation.

As far as P_DDQ goes, most of the power advantage comes from having a V_DDQ of 2.5 V, as opposed to 3.3 V for conventional SDRAM. But in a typical PC environment, the power supply provides the 3.3 V, while the 2.5 V isn't available and needs to be created on the motherboard. Again, unless an efficient regulation scheme is used to generate V_DDQ, the power-dissipation advantage is lost. So, switching regulation should be the preferred means of processing both P_DDQ and P_TT power for DDR memories.

With DDR2, V_DDQ is reduced from 2.5 V down to 1.8 V and V_TT from 1.25 V down to 0.9 V with a sink/source drive capability of ±13.4 mA.⁵ Accordingly, DDR2 memories end up consuming much less power than first-generation DDR.

For example, a DDR2-533 ends up consuming roughly half of a DDR-400.⁵ All static and dynamic observations made in the previous sections for DDR apply to DDR2. The termination scheme for DDR2 is slightly different than the one for DDR shown in Figure 1, and the termination resistors are on-chip, not on the motherboard. Still, an external V_TT termination voltage is necessary. At the much lower levels of DDR2 power consumption, linear regulators for V_TT can be used, especially if simplicity and cost are prevailing considerations over minimizing power consumption.

DUAL PWM CONTROLLER A variety of DDR power ICs is on the market. There are the ML6553/4/5 with integrated MOSFETs; the FAN5066 for high-power systems; and the FAN5068, a combo DDRx and advanced configuration and power interface (ACPI). Another device, the FAN5236, is specifically designed for all-in-one powering of DDRx memory systems. This single IC integrates a switcher controller for V_DDQ, a switcher controller for V_TT, and a linear buffer for V_REF. The switcher for V_DDQ runs off any voltage in the range from 5 to 24 V. However, the switcher for V_TT is different. It's designed to run from the V_DDQ power and switches synchronously with that switcher.

Both switchers' outputs can range from 0.9 to 5.5 V. Because the bus lines are driven with 2.5 V (DDR) or 1.8 V (DDR2) for V_DDQ and are terminated to 1.25 V (DDR) or 0.9 V (DDR2) for V_TT, the power to some extent circulates between V_TT and V_DDQ. Drawing V_TT from V_DDQ minimizes total circulating power, and thus circulating power losses. The V_TT switcher also can be shut down for standby mode.

DUAL PWM CONTROLLER APPLICATIONFigure 2 shows the typical application and the table shows the associated bill of materials (BOM) for a 4-A continuous, 6-A peak V_DDQ application. (For the table of the associated bill of materials, go to www.elecdesign.com and see Drill Deeper 10926.) Note that in Figure 2, the outer rectangle represents the FAN5236 dual pulse-width modulator (PWM), while the two smaller rectangles named PWM1 and PWM2 represent the two switchers inside the IC. Also note that in the table, the FAN5236 is called DDR controller and referenced as U1. This circuit can easily be modified to set V_DDQ at 1.8 V (via divider R5/R6) and V_TT to 0.9 V for DDR2 applications.

Setting The Output Voltage: The internal reference of the FAN5236 PWM controller is 0.9 V. The output is divided down by a voltage divider to the VSEN pin (R5 and R6). The output voltage therefore is:

0.9 V/R6 = (V_DDQ ×; 0.9 V)/R5

Output Inductor Selection: The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The standard practice is to choose minimum current of somewhere between 15% and 35% of the nominal current. At light load, the controller can automatically switch to hysteretic mode of operation to sustain high efficiency. The following equations help to choose the proper value of the output filter inductors, L1 and L2.

DI = 2 × I _MIN = DV _OUT/ESR where DI is the inductor ripple current and ?V_OUT is the maximum ripple allowed.L = \[(V_IN -­ V_OUT)/(F_SW × DI)\] × (V_OUT / V_IN)

where F_SW is the switching frequency.

Output Capacitor Selection: The output capacitors, C6 and C8, serve two major functions in a switching power supply. Along with the inductor, it filters the sequence of pulses produced by the switcher, and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, inductor ripple current (DI), and the allowable ripple voltage (DV).

ESR DV/DI

Input Capacitor Selection: The input capacitor (C1) should be selected by its RMS current rating. In DDR mode, the V_TT power input is powered by the V_DDQ output. Therefore, the V_DDQ converter load I_OUT produces the input capacitor ripple current. The RMS input current will be:

I_RMS = I_OUT(MAX)√D — D²

where D is the duty cycle of the PWM1 converter and is calculated as D = V_OUT/V_IN. In parallel to C1 is C9, a small ceramic capacitor always present at the input for high-frequency source-impedance filtering.

Power MOSFET Selection: Losses in a MOSFET are the sum of its switching (P_SW) and conduction (P_COND) losses. In typical applications, the FAN5236 converter's output voltage is low with respect to its input voltage. Therefore, the lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should thus be selected to minimize conduction losses, thereby selecting a MOSFET with low R_DS(ON).

In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, lessening the impact of its conduction loss. Q1, however, sees most of the switching losses, so Q1's primary selection criteria should be gate charge.

Layout Considerations: Even during normal operation, switching converters produce short pulses of current that could cause substantial ringing and electromagnetic interference if layout constraints aren't observed. Two sets of critical components exist in a dc-dc converter. The switching power components, which process large amounts of energy at high rates, are noise generators. The low-power components responsible for bias and feedback functions are sensitive to noise. A multilayer pc board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane, and break this plane into smaller islands of common voltage levels. For details, refer to the FAN5236 data sheet.

FUTURE TRENDS As has been the trend for many years, customers will demand more and more memory to run their ever-larger software applications. Systems such as Intel's boards for servers are already being designed with large amounts of DDRx memory. Some systems contain as much as 16 Gbytes. To power such systems, the decreased power requirements of first-generation DDR may still not be adequate, hence the move toward DDR2 memory technology.

Though we're reaching the peak of the DDR2 cycle, the industry is already buzzing about the next-generation memory technology for PCs—DDR3 memories. While DDR3 isn't expected to reach the market until 2006, vendors like Samsung have already shown prototypes of 512-Mbyte DDR3 DRAM chips, increasing speeds up to 1066 Mbits/s while reducing the voltage down to 1.5 V.

References:

1. JEDEC STANDARD JESD79, June 2000 and JESD8-9 of Sept. 1998.
2. JEDEC STANDARD JESD79-2A, January 2004.
3. DDR SDRAM Signaling Design Notes; Micro Linear and Micron Technology; April 1999.
4. Wang, Ling Ling, and Leung, Philip of Acer Labs; Tabrizi, Farhad of Hyundai Microelectronics, "DDR DRAMs Pare Down Power for Laptop," Portable Design, July 2000.
5. DDR2 low power features. Samsung AN. 10-18-2003.