Already a capable tool for RFIC simulation, verification, and analysis, the latest version of Agilent’s GoldenGate simulator delivers enhancements in performance as well as new stability and yield analysis capabilities. Version 4.4 of GoldenGate also offers improvements in wireless design verification.
Among its updates to key RF design analyses, GoldenGate 4.4 includes performance enhancements for advanced-node RFIC designs, including a 2x improvement in speed for periodic steady-state (harmonic-balance) analysis, a new single-sideband noise option, and fast envelope support for wireless virtual test benches. It also adds periodic steady-state based stability analysis that finds instabilities under large-signal conditions for oscillators and driven RF circuits, even with large extracted views.
A final major addition to the simulator’s analysis capabilities is a fast yield-contributor analysis that quickly determines circuit-yield contributors at any stage of the RFIC design flow. Performed using statistical process models from foundries, yield-contributor analysis reveals how the process variation itself affects performance. Rather than running long Monte Carlo simulations with statistical process models, GoldenGate’s yield-contributor analysis is a much faster analysis tool that delivers ±1-sigma agreement with Monte Carlo methods.
“It won’t cover the entire range of distribution,” says Paul Colestock, Agilent EESof’s RFIC planning and marketing lead. “But it will tell you the amount of variation, identify its sources, and show to what degree they impact the results.”
For wireless design verification, the tool now offers a comprehensive wireless testbench flow that links system and RF simulation for verification of RFICs. “We’re taking advantage of the breadth of wireless testbenches we already have here at Agilent,” says Colestock. “The test instruments have the specs embedded for generating complex waveforms, as well as the algorithm pieces that comprise the baseband. Meanwhile, we have dozens of libraries for every wireless standard out there.”
The idea is to package these testbenches with GoldenGate’s new Ptolemy wireless testbench-library export capability to create a wireless verification library. Once libraries and testbenches are packaged, they can be easily applied in GoldenGate as well as in the Cadence Virtuoso custom design and implementation flow.
GoldenGate performs analog mixed-signal co-simulation to accelerate RF-mixed-signal simulations with support for envelope transient analysis with Verilog-AMS. Also added are RF and package co-design capabilities that verify RFICs with package- and board-level RF passives using more than 150 new components in the Agilent Advanced Design System passive RF component library for GoldenGate.
Agilent GoldenGate version 4.4 is now available with a starting price of under $25,000.
