Graphical System Design: A Bridge to Digital Power

As the demand for higher-power and higher-precision instrumentation grows, the size requirements for these devices continue to shrink and the design complexity increases. The PCI eXtensions for Instrumentation (PXI) platform is a good example of a size requirement (3U Euro-card) that has already managed to accommodate digital multimeters, oscilloscopes and many other instruments, but has struggled to meet the traditional requirements of programmable power supplies. The reason is obvious: A volume measuring 2 cm × 13 cm × 22 cm can hardly support the transformers and heatsinks typically required in a system power supply.

Designing for PXI modules and other tightly constrained environments has been helped by two recent trends: higher-performance switch-mode power supplies and the use of digital control to regulate them. However, implementing these technologies without the combined efforts of digital, analog and software engineers can be daunting. Using an intuitive graphical system design process in National Instruments (NI) LabVIEW software can greatly improve a lone analog engineer's ability to implement the digital control necessary in these environments.

The PXI platform is a good environment in which to demonstrate design methods for digital power architectures. With limited power dissipation available to a PXI module (20 W) and tight requirements on output precision, noise, load regulation and input power, an FPGA-implemented control scheme is required. With the NI LabVIEW approach, an analog engineer can design this algorithm, prototype it in the loop and deploy it on silicon — all without VHDL programming knowledge. In addition to helping with the control scheme, LabVIEW is a common environment for developing test software for final verification or functional tests.

Planning the Control Scheme

To explain the graphical system design process with LabVIEW FPGA, a model of the digital power scheme is required. Consider the NI PXI-4110 triple-output programmable dc power supply shown in Fig. 1. The target specifications are three channels: 0 V to 6 V, 0 V to 20 V and 0 V to -20 V, all capable of delivering up to 1 A. Therefore, the total power output is 46 W. Remember that the maximum cooling capability is 20 W in that same space, so high efficiency is required in order to avoid thermal issues.

The implementation strategy taken here is a combination of a SMPS and a linear supply. The switcher can preregulate the input to get you close to the desired output, while the linear stage can regulate precisely with little noise. Then, the main source of heat is the difference between the switcher output and the linear output. For example, if the switcher emits 22 V and the user requests 20 V at 1 A, it dissipates 2 W ((22 V - 20 V) × 1 A). However, if the suggested output is 5 V at 1 A, much more heat will be generated.

To provide tight regulation of this switcher voltage, the switching supply must include closed-loop control of the output voltage. The more discrete voltage levels available at the output of the switcher, the lower the power dissipation becomes in the pass element of the linear regulation stage.

To provide closed-loop control, the voltage from both stages needs to be fed back to the switcher control, so it can make a decision about where to set the switcher's output voltage. Because isolation is a requirement, the design uses high-performance analog-to-digital converters (ADCs), highly integrated logic devices and fast digital interfaces to implement the digital control. This leverages circuitry already in place for monitoring and measurement. The diagram in Fig. 2 depicts the basic implementation of this concept.

The scheme is intended to control the voltage difference between the SMPS and the linear regulator in order to carefully manage the maximum power dissipated by the pass element in the linear power supply, which is equal to the voltage difference multiplied by the maximum output current.

For example, if the difference is 2 V and the maximum output current is 1 A, the control element would dissipate 2 W in the worst case, as previously shown. The control logic can be implemented as a simple and efficient algorithm such as proportional-integral-derivative (PID):

P = KP 3 (SP[n] - PV[n])

I = KI 3 (SP[n] - PV[n]) + KI 3 (SP[n-1] - PV[n-1])

D = KD 3 (PV[n] - PV[n-1])

OUTPUT = P + I + D,

where SP equals setpoint, PV equals power across linear stage, KP equals proportional gain, KR equals integral gain and KD equals derivative gain.

One major disadvantage of this approach is that, without a load at the output, the control logic generates a PWM signal with the minimum duty cycle. This is equivalent to having a high output-impedance source supplying power to the linear stage. Thus, a load transient or raising the output voltage may collapse the voltage across the linear pass element to zero, taking the output into an unregulated state. These two cases are illustrated in Fig. 3.

A second problem related to this approach is that the time it takes to recover from this kind of crash is proportional to the sampling rate of the digital controller. Due to the isolation between the controller and the switching power supply, the sampling period is set by the rate of the data transferred through the digital isolators. Multiplexing a single ADC for several measurements also contributes to increase the total sampling period. This may leave room for only a few kilohertz in order to keep the costs down by avoiding extra-high-speed ADCs and a dedicated feedback path for recovering from this condition.

In this implementation, the voltage may change too quickly to be effectively managed by the control loop. A better solution is power control instead of voltage control. Controlling power has two advantages that the voltage-control approach lacks. First, it requires less bandwidth and decreases the output impedance of the switcher. Second, controlling power comes at almost no extra cost because current is often measured along with voltage.

Although power can change very quickly, the main concern in space-constrained designs is temperature rise. An increase in temperature, caused by the buildup of heat from the linear pass element, is a relatively slow process, so that the controller has enough time to correct this error. Thus, it is possible to use a slow control-loop sampling frequency.

Furthermore, because the power dissipated by the linear stage is being controlled, the output impedance of the SMPS reaches its minimum value when operating in low power, as opposed to the approach of controlling voltage, which leads to the highest impedance value at the SMPS output under the same condition. This occurs because the power tends to be zero when the current flowing to the load is close to zero. Therefore, the duty cycle of the PWM signal reaches its maximum, increasing the switcher voltage in an attempt to get the linear stage to dissipate some power. Thus, whenever there is a transient, there is enough voltage applied across the pass element of the linear stage to rapidly compensate for it (Fig. 4).

Designing the Control Loop

Having identified an appropriate algorithm for control logic (PID) and an effective form of loop control (power-based), it's now possible to design the digital control loop. The implementation of a digital algorithm in an FPGA can require several lengthy iterations among the tasks of mathematical definitions, simulations, review by the analog and digital engineers, and testing. Using this labor-intensive process to discover and correct design bugs can be quite time consuming.

Hardware-in-the-loop simulation has helped reduce development time through a PC-controlled process that serves as a substitute for one or several portions of the final design. The goal is to have the computer simulate several scenarios (stimulus and control algorithms) before the design is actually deployed into the real application. This improves the debugging, validation and overall cost of implementation.

LabVIEW FPGA offers a method for achieving hardware-in-the-loop simulation. The power of a graphical programming and modeling language allows for quick prototyping and deployment into real-world applications. For digitally controlled power supplies, this means that digital control systems can be prototyped and tested in a computer without concerns about FPGA size or the time required for the process of writing and synthesizing large volumes of VHDL code. After the graphical code has been validated and tested, it can be deployed onto an FPGA directly from LabVIEW, so the control loop runs entirely independently from computer software in the actual application.

Consider the power-control scheme of the power supply shown in Fig. 5. The power-control approach takes care of the low- to high-power transients, but not medium-power transients. During medium-power transients, there are already smaller voltages across the linear regulation stage, and the output impedance of the switching stage is higher than in the previous example. Under these conditions, it is still possible to collapse the voltage across the linear stage, so a modification to this algorithm is in order.

Because of the limited sampling frequency, the PID controller may not be fast enough, as it is going to lag for at least one sampling period before it can respond to this type of transient. If the time constant imposed by the output impedance of the switcher and the load is faster than the sampling period, collapsing of the output occurs as shown in the PID control waveforms in Fig. 6.

However, providing a solution is very simple once the controller is in the digital domain, because it only requires the addition of a feed-forward algorithm. The feed-forward algorithm leads the PID in transients, increasing the power to the maximum so the output never collapses. The PID can then regulate to reduce the power. These actions can be seen in the PID with feed-forward waveforms in Fig. 6.

Using LabVIEW, this algorithm can be implemented quickly, and it works under a set of conditions defined by the designer. Examples of such conditions are low voltage across the linear stage, or output-parameter changes requested from the user.

This feed-forward algorithm has been added as a case structure in Fig. 7. The output then becomes an open-loop control that can boost the switcher power to the maximum. This is the equivalent to a step function, but the feed-forward algorithm could actually be any arbitrary function to fit a particular operation; it can be either a self-contained, closed-loop process or the result of a different process.

Once these modifications to the algorithm have been implemented in LabVIEW and simulated on the host PC, they can be deployed to the FPGA that controls the power supply for final validation and system integration.

During cross-system validation, other issues that force further tweaking of the algorithm may arise. Taking the previous example, in the case of using a step function for the feed-forward algorithm, an excess of input current may blow input fuses or affect overall system performance. To limit this input current, the step function can be substituted with a ramp function (or another soft-adjust function) that is not so fast it blows fuses or exceeds the current rating (Fig. 8) and not so slow it fails to address the transient-response problem that existed for intermediate voltages.

Design Deployment

Adjusting this ramp time can be as simple as changing a variable until the current spike does not go above the limit set by the system ratings or other design constraints. You can do this in real time by manually changing values in the host PC while running the hardware-in-the-loop simulation. When the desired value has been found, the algorithm can be redeployed to the FPGA for final verification.

Therefore, if output is close to collapse or the user changes output parameters, then:

P = KP 3 (SP[n] - PV[n])

I = KI 3 (SP[n] - PV[n]) + KI 3 (SP[n-1] - PV[n-1])

D = KD 3 (PV[n] - PV[n-1]).

OUTPUT = ramp function, else OUTPUT = P + I + D.

The main advantage of using LabVIEW FPGA for simulation and hardware-in-the-loop testing is the ability of the analog engineer to rapidly change and then deploy the model to the FPGA for production. As electrical, mechanical and thermal constraints continue to challenge power-supply engineers, this flexibility offers a real-world solution to difficult digital-control implementations.