New test points help contain growing test costs
Recent and continuing trends in the semiconductor industry pose challenges to IC test-data volumes, test application times, and test costs. The industry has thus far succeeded in containing test costs through constant improvements in the efficiency of DFT technologies. One example is seen in the rapid adoption of hybrid ATPG/logic built-in self-test (LBIST) in the fast-growing automotive IC market. The once-separate ATPG and LBIST technologies have merged to the point where compression IP is being reused to apply BIST tests. Now the latest leap in test efficiency is a new kind of test point that works with hybrid ATPG/LBIST with more efficiency than test points for either separately. Test points that target both scan compression and BIST significantly cut test time and cost with no loss of coverage.
About Hybrid ATPG/LBIST
Embedded ATPG compression technologies have been the standard method of manufacturing test for many years. LBIST was originally introduced for board, system, and in-field tests—a key requirement in mission-critical automotive ICs. Increasingly, both technologies are combined to achieve the best possible results for both system test and IC manufacturing test.
The huge growth in automotive chip design has prompted a focus on high quality (zero defect) and ISO 26262 compliance, which has led to the rapid adoption of hybrid ATPG compression/LBIST solutions. While LBIST allows for the field testing of circuits, ATPG offers high precision of pattern application. “Precision” of pattern application means that ATPG can provide very specific values with each pattern, which lets it apply tests on specific paths or to control individual clock gating elements throughout the design. This means that you can get better defect detection through specialized fault targeting including timing-aware, cell-aware, path-delay, bridge, and other types of ATPG. The combination of these two testing methods in a hybridized version allows testing of automotive IC designs in various scenarios: wafer, packaged, and in-system.1
Using both compressed ATPG and LBIST together once had the clear drawback of increased chip area for logic test. The LBIST LFSR (linear feedback shift register) and the compression decompressor for ATPG (as well as MISR and compression compactor) traditionally used different logic, even though their functional purposes are similar. There are now solutions that combine the logic from embedded compression ATPG and LBIST to enable this hybrid ATPG/LBIST approach without the area penalty. Figure 1 illustrates the combined logic architecture of hybrid TK/LBIST. The compression (embedded deterministic test) and LBIST share a majority of the decompressor/LFSR and compactor/MSIR logic.
Next-generation test points for hybrid ATPG/LBIST
Many devices require ATPG compression and logic BIST, but neither ATPG nor BIST test points have been well suited for use in a hybrid ATPG/BIST environment. Now there is a new hybrid test-point technology that improves ATPG compression as well as random pattern coverage.
Test points targeting BIST-tested circuits have been around for over a decade. They target areas of the circuit to reduce random pattern resistance, helping to increase the test coverage of the circuit with fewer patterns. Figure 2 illustrates a BIST test-point circuit. To propagate faults from the cone of logic through gate G1, the output of gate G2 needs to be set to 1. With pseudorandom patterns driving gate G2, the probability of having 1 on its output is relatively low. Inserting a test point between G1 and G2 alleviates this situation.
LBIST test points break up areas within the circuit that are random-pattern-resistant, like large blocks of logic focused on encoding or decoding. Circuits with large numbers of inputs that must be controlled to propagate faults may present a controllability problem when random patterns are applied, tests for which ATPG may not have any issue. Circuit structures with low fan-out may make it difficult to effectively observe the faults within; you may need many more BIST patterns to properly sensitize fault propagation paths, or you may choose observe points for direct observation. ATPG may have an easier time propagating such fault effects. Test points for LBIST may be deployed in order to decrease random pattern resistance to allow reaching coverage goals or reaching them earlier. However, test points targeted for improvements in BIST tests are not as effective at reducing pattern counts for deterministic ATPG tests as test points that are targeted specifically for reduction in ATPG pattern counts.
Test points targeting ATPG test pattern count are relatively new.2 These automatically inserted gates allow parallel logic cones to share the same ATPG patterns. EDT test points help to control growing vector counts by reducing the number of vectors needed for the same original coverage. EDT test points also allow improvements to product quality by freeing up tester memory for newer test types such as cell-aware-based tests. For a more detailed discussion of EDT test points, see the technical papers from Intel3 and Broadcom4. To reduce pattern count, EDT test points can, for example, resolve controllability conflicts in which a single node is used to drive both logic 1 and logic 0 to apply test patterns to different paths.
Pattern-count-centric test points work in different ways, for example, by breaking up controllability conflicts, where a single node may be required to be driven to both logic 1 and logic 0 to apply test to different circuit paths.
Figure 3 illustrates an EDT test-point circuit. Suppose T1 test patterns are needed to detect faults propagating to gate G3, so the other input must be set to 1. Setting this node to 1 precludes the detection of faults propagating through G4. Likewise, setting the other input of gate G4 to 0 blocks propagation of faults through G3. Faults in both groups cannot be detected by the same test patterns so the total number of test patterns will be equal to T1 + T2. By inserting an EDT test point on one of the stem branches, this conflict can be resolved and detection of faults propagating to both gates can be detected. For example, a test point on the left branch achieves independent 1-controllability of this line; a test point on the right branch allows 0-controllability of that line. The result is that the number of test patterns becomes equal to max (T1, T2), or, if T1 ≈ T2, potentially reducing the pattern count by half.
Based on experiments, EDT test points reduce ATPG-based test pattern counts but are not as effective in BIST mode since they cannot guarantee desired random testability. While the benefits of the hybrid ATPG/LBIST approach are significant, neither EDT nor LBIST test points are exclusively suitable for hybrid test solutions. This mutual incompatibility meant that customers implementing a hybrid ATPG/LBIST approach would need to run test point insertion twice in order to achieve the best result for both ATPG and BIST tests. This incompatibility of both types of test points motivated the development of a novel hybrid test-point insertion scheme designed to both reduce deterministic pattern counts and improve fault detection by means of the same minimal set of test points.
How hybrid ATPG/LBIST test points work
The new hybrid ATPG/LBIST test-point technology combines all the benefits of EDT and LBIST test points and works better than either type of test point separately. A 2016 ITC paper offers a more detailed discussion of hybrid test-point technology.5
This most recent advancement in test-point technology combines the co-targeting of multiple test point goals (pattern count reduction and BIST coverage) with more advanced test-point analysis and insertion algorithms.
The results based on these new test points are better than the sum of both previous test points in many cases. Table 1 shows the improvement in test coverage with hybrid test points over EDT or LBIST test points separately. The average test coverage improvement between LBIST and hybrid test points is 3.25%.
Hybrid test points are also better than EDT test points at reducing ATPG pattern count, as Table 2 illustrates. The ATPG baseline columns show the test coverage (TC) and pattern count (PC) with no test points inserted. The ATPG PC @baseline TC columns show the pattern counts for each of three test-point types, with the same test coverage at baseline. The red-outlined columns calculate the difference between baseline PC and PC with each of three test-point types. Hybrid ATPG/LBIST test points outperform either EDT or LBIST test points for pattern count reduction.
Hybrid test points are currently being evaluated at several large semiconductor companies as replacements for separate LBIST and ATPG test-point insertion in hybrid ATPG/LBIST testing strategies. All are finding that the run-times of the newer algorithms targeting LBIST test points are far faster than previous algorithms, providing savings of 20X on average. Improved LBIST coverage for automotive customers targeting in-system test means 90% test coverage targets are achieved faster.
Summary
Hybrid ATPG/LBIST test points are a new DFT technology that reduces deterministic test-pattern counts and improves random testability. This is achieved by deploying EDT and LBIST test points in a hybrid manner which work synergistically in designs where on-chip sequential test compression is integrated with logic BIST infrastructure. Hybrid test points offer high-quality manufacturing test with reduced test application time, an important consideration when running in-system tests for applications such as automotive ICs.
About the author
Jeff Mayer is a technical marketing engineer for Mentor Graphics Tessent DFT and yield analysis division.
References
- Press, R., and V. Neerkundar, “Improve Logic Test with a Hybrid ATPG/BIST Solution,” Mentor Graphics Whitepaper.
- Pateras, S., “EDT Test Points,” Mentor Graphics Whitepaper.
- Acero, C., et al., “Embedded Deterministic Test Points,” IEEE Transactions on VLSI Systems, 2017.
- Konuk, H., et al., “Design for Low Test Pattern Counts,” Proceedings of the International Test Conference
- Moghaddam, E., et al., “Test point insertion in hybrid test compression/LBIST architectures,” Proceedings of the International Test Conference 2016.