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Chipsets Essential to Projecting Gaming Displays Anywhere
Sept. 23, 2024
Related To: Electronic Design
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Traditional gaming monitors may go the way of the cathode-ray tube as ultra-short-throw projected gaming-display technology enables compact devices to project displays anywhere. While the new technology shows promise for any high-resolution media applications, it’s particularly suitable for gaming, in which users interact in real time with the display content.
An optimal gaming experience requires high frame rates, low display latency, and variable refresh rates. Faster frame-rate capability is particularly important for reducing blur. As seen in Figure 1, a still image captured from a 60-Hz frame-rate display (left) has considerable blur, while the same image from a 120-Hz frame-rate display (center) shows significant improvement. Modern chipsets incorporating the latest digital-light-processing (DLP) display technology can support frame rates to 240 Hz, virtually eliminating blur (right).
Display latency specifies the amount of time necessary for the display to update in response to a controller input, with latencies less than 20 ms considered acceptable for gaming. Latency depends on delays throughout the entire data-processing pipeline, including any image-processing steps upstream of the display controller.
As an example, traditional DLP display controllers use a double-frame buffer architecture that adds a one-frame delay. In contrast, one modern DLP display controller employs a new rolling frame-buffer architecture that can significantly reduce latency when combined with a digital micromirror device (DMD) that offers fast switching speed. The combination can reduce latency down to 1 ms, as measured at the corner of the image from which new frame data enters.
Another key aspect of gaming applications is support for variable-refresh-rate sources, in which refresh rate varies in accordance with the load on the graphics processing unit. A display without variable-refresh-rate support driven by a variable-refresh-rate source will exhibit artifacts like stuttering as latency varies from frame to frame and frames are displayed out of sync. A display with variable-frame-rate support will show new frames without delay as they arrive from the source, regardless of whether or not the source is dynamically changing the frame rate.
Texas Instruments offers its DLP Pico product lineup to support a wide range of display applications. Supported resolutions (see table) extend from ninth High Definition (nHD) through 1080p Full High Definition (FHD) and on to 4K Ultra High Definition (UHD), with mirror arrays ranging from 0.1 to 0.47 inches. All DLP Pico display chipsets include a controller and DMD, while most also include a power-management integrated circuit (PMIC).
A recent addition to the lineup is the TI DLPC8445 high-resolution controller, which, in conjunction with the DLP472TP DMD, supports up to 4K UHD displays at up to 60 Hz; up to 1080p 2D displays at 240 Hz; and up to 1080p 3D displays at 120 Hz. TI calls the DLPC8445 the first DLP display controller to implement variable-frame-rate support. Figure 2 shows a complete chipset including the DLPC8445 controller, the DLP472TP DMD, and the DLPA3085 PMIC.
The DLPC8445 controller includes an internal Arm processor with 52 configurable general-purpose input/output (GPIO) lines, a pulse-width-modulation (PWM) generator, capture and delay timers, and USB 2.0, SPI, I2C, UART, and interrupt controllers.
The controller also includes a warping engine with 1D, 2D, and 3D keystone correction, and it offers additional image-processing functions including frame-rate multiplication, color coordinate adjustment, white-color temperature adjustment, and read-side spatial-temporal multiplexing. In addition, there’s integrated support for 3D displays and a rolling buffer for reduced frame latency, as well as serial flash for storing PWM sequences.
The DLP472TP DMD is a 0.47-in. diagonal spatial light modulator that consists of an array of aluminum micromirrors. The DMD, an electrical-input, optical-output, micro-optical-electrical-mechanical system (MOEMS), offers fast switching speeds to enable each micromirror to display four distinct pixels on the screen during every frame, resulting in a full 3,840- × 2,160-pixel image. The electrical interface employs low-voltage differential signaling (LVDS). The DMD consists of a two-dimensional array of 1-bit CMOS memory cells organized in a grid of M memory-cell columns by N memory-cell rows.
Optimized for DLP Pico projector systems, the DLPA3085 PMIC supports a variety of high-current LEDs through the control of external 16-A power FETs. Figure 3 shows the PMIC as well as the controller and DMD in a typical projector module under the control of a front-end chip.
The PMIC generates internal supply and reference voltages, controls illumination, and generates timed high voltages for the DMD. It also includes auxiliary low-dropout regulators (LDOs) to generate fixed voltages for customer use.
Choosing a chipset is just one aspect of the multistep process necessary for complete display application development. The first step is to refine your display integration concept through the analysis of available display technology and a review of application examples. Then you can proceed to the next step—choosing and evaluating a chipset, such as the DLPC8445 controller, the DLP472TP DMD, and the DLPA3085 PMIC.
After selecting a chipset, you will need to specify a optical engine. Typically, you can purchase a suitable optical engine from a variety of manufacturers. With the chips and optical engine nailed down, you will want to evaluate the complete supply chain, including any system integrators or design houses you may intend to use. The final step is to determine best practices for manufacturing readiness.
To help you get started, TI offers evaluation modules that let you assess image quality and modify chipset software parameters, and the company’s experts can provide the guidance necessary to complete a successful manufacturing-ready short-throw projected gaming-display design.
