These days, electronic systems and products are always looking for increased communication speed and lower power consumption. Emerging silicon photonics technology holds a great deal of promise in computing and communications for sheer performance, reduced power, and overall increases in bandwidth. Early applications to short-run data communications in the data center, described by Intel and Cisco among others, are capturing attention in the press. With the world headed toward the Internet of Everything, more capable and efficient server farms are interesting to many.

What Is It?

According to Wikipedia, photonics includes the generation, emission, transmission, modulation, signal processing, switching, amplification, and detection or sensing of light. Photonics is not new, but historically photonics components have been manufactured using boutique processes tailored for each application. What’s new is the drive to leverage high-volume silicon-based semiconductor manufacturing foundries and processes to build chips that can create, sense, modulate, and transmit light.  

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Fortuitously, with relatively minor modifications to foundry processes and some EDA tool enhancements, the existing CMOS fabrication infrastructure can be used to design and construct complex circuits that integrate electronics and photonics on the same silicon chip. These new silicon photonic chips can transfer information seamlessly between the electronic and optical domains. By leveraging the existing CMOS ecosystem, they can be made in huge volumes and at much lower cost that previously possible.

What Does It Bring To The Electronics Party?

Electrons and photons have different properties that have been used separately to enable many systems capabilities. Electrons have been used since the 19th century for communications and since 1937 in electronic computers. Fundamentally, two electrons cannot be in the same place at the same time due to their strong interaction. This characteristic of electron charges is exploited to build transistor switches, the basis of all computers and digital signal processing.

In contrast, many photons can be in the same place while behaving independently in some respects. This makes it possible to transmit terabits of data per second through a single optical fiber—not by creating a single stream of data, but by transmitting many simultaneous streams through the fiber simultaneously. Compared to a single fiber optic cable, electronic data transmission requires many parallel cables and an associated collection of power-hungry driver electronics. With this potential leverage in the data center, heavyweights like Intel, IBM, and Cisco are publishing their plans for commercialization of silicon photonics, and we expect this to be one of the first volume applications of the technology.

Beyond data communications there is a wide range of photonic applications under development including bio-sensing, nano-optomechanics, optical gyroscopes, and many others. Each of these applications exploits a unique property of light to enable new capabilities, higher performance, or lower power consumption. When photonics and electronics are combined into a single integrated system, they can enable solutions that were previously unachievable or cost prohibitive.

Challenges To Solve

Over the last decade or so, IME, IBM, OpSys, Plat4M, and other consortia/companies have labored with growing success to apply high-volume CMOS foundry manufacturing processes to silicon photonics. They have been successful in using silicon manufacturing to fabricate waveguides, light multiplexers, photodetectors, and the like. The next stage in achieving maturity of the technology is to put a robust design enablement infrastructure in place.

One of the key ingredients is the availability of device models, just as with ICs. Device models describe the underlying behavior of the standard components of photonics, allowing designers to use EDA tools to describe a collection of interconnected components and to predict the behavior of the overall design. The leading foundries, their customers, and EDA partners are now working on making these models available. 

Due to the nature of light, silicon photonics requires precisely drawn and characterized curved structures (see the figure). This is somewhat different than electronic circuits, which are typically defined in terms of orthogonal shapes, i.e., parallelograms. The need to deal accurately with curves creates one of the most pervasive issues for adapting IC design tools and foundry processes to photonics.

Silicon photonic interconnects, i.e., optical wave guides, require very precise curves to ensure that the structures will perform as expected for a given wavelength of light connecting photonic devices. The challenge is compounded by the fact that Spice, the netlist format used in traditional IC design, has no real way to precisely describe a photonic interconnect. It only deals with devices and device pins. We need a language and tools to verify that pre-defined components (i.e., photonics intellectual property) and interconnecting waveguides will work together in each new design context.

Of course, even when the design is verified as correct and accurate, what you get in silicon is still subject to the manufacturing variation inherent in the lithography process. What you’ve drawn, characterized, and simulated in the tools may be very different than what is actually on the wafer. Electronic circuits have a degree of immunity to distortion in the shapes printed on the wafer. However, photonics circuits are very sensitive to the exact shapes of devices and waveguides implemented in silicon, so these variations must be minimized or considered when projecting the behavior of the photonic system.

Today, most EDA tools perform layout generation, physical verification, circuit verification, design for manufacturing (DFM) analysis, and more using a rectilinear (also known as gridded or Manhattan) database format like GDSII. Mask patterning tools are used to create the masks for the IC lithographic process on GDSII, as do the silicon foundries. This means that curved photonic structures must be represented by step-wise linear shapes (like the “jaggies” on a computer screen), introducing many tiny straight edges.

When the standard design rules for a typical CMOS process (where everything is expected to be Manhattan) are applied to a curved photonics design, it can result in many design rule checking (DRC) errors. Also, the typical layout versus schematic (LVS) tools do not adequately support silicon photonic devices with their curved structures because device models have not yet caught up with the requirements.

Real Progress

Significant effort is being expended to enable the EDA infrastructure to handle accurate representations of silicon photonic waveguides and devices during layout, physical verification, and manufacture in the existing foundry ecosystems. For example, the Mentor Pyxis custom IC design platform has been extended to provide silicon photonics interconnects with the required waveguide properties as a basic layout construct.

This lets designers place components from a silicon phonics library and connect using schematic-driven layout generation and other automation. Extensions to Spice along with integrations with tools from third parties like Lumerical is enabling the definition of device model libraries and simulation of both electronics and photonics behaviors within the EDA environment.

The equation-based DRC facilities of Calibre nmDRC are being employed to define accurate photonics-specific design rules and to handle non-rectilinear geometries during verification. Mentor is working with foundries such as OpSys and STMicroelectronics to create photonics design rule decks. Other features such as real-time checking, visual error debugging, and automatic waiver management also help IC designers efficiently deal with design rule violations when they occur.

Calibre nmLVS has been enhanced to support device models and connectivity checking for photonics designs by employing its user-defined device parameter capabilities. Litho simulation and hot-spot detection capabilities in Calibre LFD are also being extended in collaboration with foundries to help ensure that the design can be faithfully produced onto the wafer within the margins required for proper operation.

A lot of progress has been made to bring mature EDA design flows to silicon photonics designers. This will help ensure that the design timelines for ICs including photonics subsystems will be consistent with the design of associated electronics and that electronic-photonic systems-on-chip (SoCs) will perform as expected. Test chips have been generated using the new tool flows, and foundries are gearing up for full production. Beyond that, it’s up to IC designers to conceive of new applications that create value for their customers and profit for their companies.

Michael White is the product marketing director for Mentor Graphics’ Calibre Physical Verification products.  Prior to Mentor Graphics, he held various product marketing, strategic marketing, and program management roles for Applied Materials, Etec Systems, and the Lockheed Skunk Works. He received an MS in engineering management from the University of Southern California and a BS in system engineering from Harvey Mudd College.