ARM Extends Cortex-R Series to Handle 5G
5G is still on the horizon, but ARM’s new Cortex-R8 has arrived to handle this more demanding application (Fig. 1). It follows from the Cortex-R4, -R5, and -R7 that have addressed the needs of automotive, LTE, and LTE Advanced applications. The Cortex-R8 provides a significant performance boost needed to handle 5G.
The Cortex-R8 uses an 11-stage pipeline with a super scalar, out-of-order (OoO) architecture based on the ARMv7-R standard. It supports up to four cores and each core can have up to 2 Mbytes of tightly coupled memory (TCM). Memory and buses are protected by ECC and parity.
The TCM can be used for cache and local memory so deterministic interrupt routines can be contained in it. The Cortex-R architecture supports a low-latency interrupt mode (LLIM). The memory protection unit handles up to 16 regions.
The hardware supports SIMD instructions for very high-performance DSP and media functions. The architecture supports IEEE754 double-precision and single-precision floating point.
The Cortex-R family supports lock-step mode (see “Multicore Processor Tackles SMP, AMP and Lock Step Mode” on electronicdesign.com). This links a pair of cores. It is useful in safety-critical and fault-tolerant applications and it can be applied on a per-core basis. Systems can be configured in asymmetric multi-processing (AMP) mode or symmetric multi-processing (SMP) mode.
