Processor power efficiency is almost neck-and-neck with performance these days. For mobile, it means longer battery life. For the data center, it means lower costs and less infrastructure. For many designs, power efficiency is simply a matter of making something practical.
Reducing voltages is one way to reduce power consumption in electronics. That has worked as we moved from 12 V to 5 V to 3.3 V and so on. However, the challenge becomes significant when reaching subthreshold values.
To find out how Ambiq Micro solved the problem, I spoke with Mike Salas, vice president of marketing, about subthreshold power-optimized technology (SPOT) and what it means for the future of MCUs.
This file type includes high resolution graphics and schematics when applicable.
Wong: Can you tell us about your new microcontroller and what makes it unique?
Salas: Our new Apollo MCU family is the industry’s first MCU to rely overwhelmingly on subthreshold transistor operation. It is our core belief that low energy has replaced performance as the driver for the industry, and we are using our patented technology to demonstrate this for the first time at the MCU level. This has given reductions in energy consumption down to 30 µA/MHz in active mode and 100 nA in standby for a 24-MHz ARM Cortex M4-F MCU using our Subthreshold Power Optimized Technology (SPOT).
The 24-MHz maximum clock speed that was chosen for Apollo was not driven by any limitation of the subthreshold technology, but was chosen as the sweet spot in the tradeoff between energy and performance. This frequency was more than enough for our key target markets and it gives us an impressive energy profile. Our customers guided us to that number—we could have taken this up to 100 MHz if we wanted to. Mind you, there is a point where subthreshold is not practical any more. For example, you can’t build a gigahertz-class processor using subthreshold techniques.
Wong: How does SPOT work?
Salas: In the traditional way of thinking, there is a threshold voltage where circuits are considered “on” and anything below that was considered “off.” At its most basic level, SPOT is about the ability to operate at voltage levels far below what is considered normal. In most competing products, this means driving transistors up to 1.8 V in order to create an “on” state. For analog, “on” means biasing to a point with feedback keeping all of the poles where they’re supposed to be so that it’s stable. But it’s not as binary as one might think.
Even below the threshold voltage, at around 1.0 V, the reality is that current flows in the region that people think of as off, and this subthreshold leakage has not been considered a good thing. So we reconsidered the basic assumptions—what if there was a way to derive an “on” signal from that current? The implications of this are huge, because the dynamic energy is directly proportional to the square of the voltage, which becomes the greatest lever for reducing the power. So operating at 0.5 V gives a 13X reduction in power, and if you are even more aggressive and use a subthreshold voltage of 0.3 V, you get a 36X improvement.
That's what Ambiq has focused on—challenging the conventional wisdom. We start off with the assumption that in any design we will use SPOT throughout the device, and then we keep making intelligent decisions about where that’s not feasible or not needed. In some cases, a supertheshold voltage is perfectly fine. For example if it’s something that just occurs once at boot up, then those transistors can be left entirely in the traditional superthreshold domain, since there will be no material impact to the overall energy consumption of the device. In other areas where subthreshold is not used, perhaps for performance reasons or the fact that you need to get the signaling information more quickly, we start dialing the voltage up to the point where we feel that we’re getting enough performance while still being as low energy as possible.
What you end up seeing in Apollo is a very small portion of the device operating in superthreshold, with the majority of it operating in the nearthreshold and subthreshold domain. One additional critical area for energy optimization is the clock tree. We actually have a fairly complex timing infrastructure built into the chip. Of course, there are many other areas where energy optimization can occur. For example, we use a fair amount of asynchronous circuits that help with energy efficiency.
Wong: Has SPOT been used on other products?
Salas: We developed a real-time clock (RTC) using SPOT that has been out since 2013. We have shipped millions of units since then. Through that work, we learned a tremendous amount about timing and clocking that could be used in the MCU design.
When we first developed this device, we looked at other RTC devices and found we could get a 7X to 10X reduction in power. For example, we can operate as low as 14 nA when running an RC oscillator. We then created special techniques to periodically autocalibrate an RC oscillator to a crystal, which resulted in a supply current of 22 nA. Therefore, you get the best of both worlds—very low power with fairly high accuracy. Even in crystal mode, for maximum accuracy, the power consumption is still only 50 nA.
At the time the RTC was introduced, many applications would use a microcontroller’s embedded clock to power gate the rest of the system. These MCU devices were typically consuming 600 to 700 nA, so the ability to use an Ambiq RTC to reduce the standby current down to 20 to 50 nA is a tremendous capability.
However, we also needed to provide a power-gating capability to shut off the rest of the system. As a result, we added extensive power-management features for off-chip components, such as an integrated power switch, a system sleep manager, reset monitors, and so on. We brought all of that knowledge into the MCU, so the RTC turned out to be a compelling stepping stone for us.
Wong: Does your implementation require any special changes to the typical CMOS flow or devices?
Salas: No. Our implementation uses standard CMOS technology. This was actually very hard to do, as it required a thorough understanding of the leakage characteristics at low voltages. These are not accurately modeled by the fabs, because they don’t expect people to be operating at voltages that low. Since 2005, we have run test chips and shuttles to really model these subthreshold domains and how they vary with temperature, process drift, and the effect of noise. All of these parameters are highly sensitive at these low-voltage domains, so a lot of work and modeling was done to really understand the effects.
The harder thing to do, then, was to create a set of dynamic adaptive circuits to overcome the problems that existed in these subthreshold domains. By truly understanding the subtheshold effects, and in turn building new models and custom cell libraries, we were able to successfully create circuitry that was very dynamic and very adaptive, to help overcome some of the bad effects we see in the low-voltage domains
The back end of the process is also a challenge. We wanted to use industry-standard testers, but these don’t test at our picoamp and nanoamp operating levels. So we had to create a special load board, which was finely tuned and specially adapted to measure the subthreshold levels, and then affix that to industry-standard testers. The power-measurement challenge extends all the way up to the evaluation-kit level, as even lab equipment won’t measure these currents. Consequently, we had to create a custom current ammeter board that’s mounted on the kit so that customers can see accurate current levels. It took a complete re-imagining of the entire design flow, from the transistor all the way to the evaluation kit.
Wong: Can SPOT be applied to the RAM and flash in your design?
Salas: In Apollo, we did not attack the memories using SPOT. If you look at the existing power numbers on the Apollo MCU, the majority of what remains is in the memories themselves. We consciously decided to leave the memories alone and use standard off-the-shelf structures in this first instantiation of the product.
The key is that you can’t change the bit cell. There are lines that you draw—standard CMOS, standard testers, don’t change the SRAM bit cell, etc.—but even then, there are still many other ways to reduce the power. If you look in the future, you can certainly see things you could do with SRAM, which is an area we will be exploring in the future.
Wong: How does it scale with generations of process technology?
Salas: Subthreshold technology definitely scales, and we will benefit from the shrink of the technology node. At any given node, our techniques offer a fairly dramatic improvement over all other implementations. It will take some work to scale the transistors, but not as much as you might think. Much of the modelling work is transferrable to the smaller geometries, and some of the characteristics stay similar, so we can leverage a large proportion of the work we have already done.
To bring the product to market in a timely manner, we made certain concessions in several areas. For instance, we used near threshold voltages for margin reasons in some cases when a subthreshold voltage would have, in fact, been achievable. Therefore, we left ourselves plenty of headroom to drive power consumption down even further. As the process scales down and we can reduce the subthreshold voltages, it gives us an even lower power base to work from. It also provides more leakage current as well as more performance.
This file type includes high resolution graphics and schematics when applicable.
It really does completely change the way you think about process and process technology. As we drive the geometries to be more aggressive, we get the dynamic benefits. However, that's usually at the expense of leakage current. You see that in the market today, with devices that are either good in sleep mode or good in active mode, but not both. It requires a completely different way of how we operate. In this case, the shrink gives us a floor that’s lower than all of the other devices, so we really benefit from scaling the technology curve.
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