What you’ll learn:
- What’s changing between PCI Express Gen 5 and Gen 6?
- Why PCIe Gen 6 is important.
- What features PCIe Gen 6 brings to the table.
PCI Express (PCIe) is ubiquitous and the interconnect for processors and peripherals. It provides high-bandwidth data exchange using one or more high-speed serial link pairs. PCI-SIG has released the PCI Express 6.0 Specification, so now developers can build compatible solutions.
I talked with Richard Solomon, PCI-SIG Vice President, about the differences between the new PCIe Gen 6 standard and the previous PCIe Gen 5 (watch the video above). This includes a discussion about the use of PAM4 versus non-return-to-zero (NRZ) encoding.
PCI Express Gen 6 Features
Some of the new wrinkles in the PCI Express Gen 6 standard include:
- 64-GT/s raw data rate
- PAM4 (4-level pulse amplitude modulation) signaling
- 242b/256b encoding
- Lightweight forward error correction (FEC) and cyclic redundancy check (CRC)
- FLIT (flow control unit)-based encoding
A x16 interface delivers a throughput of 256 GB/s. Like previous versions of PCI Express, PCIe Gen 6 maintains backwards compatibility. This includes all prior versions.
The move to PAM4 is significant especially for future versions. Building PCIe Gen 6 silicon tends to be more challenging as prior versions don’t use PAM4. Likewise, the new FEC and CRC support is designed to mitigate the bit-error-rate increase associated with PAM4 signaling.
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The FLIT-based encoding is also part of the PAM4 modulation scheme. It works in tandem with the FEC and CRC; thus, the 2x bandwidth improvement can be real. FLIT also required an updated packet layout to simplify processing and hardware design. In addition, it allows for additional functionality to be included in the packet.
PCI Express Gen 5 Features
PCI Express 5.0 offered a number of improvements over Gen 4, including:
- 32-GT/s raw data rate
- NRZ signaling
- 128b/130b encoding
PCIe Gen 3 through Gen 5 utilize 128b/130b NRZ encoding, while earlier versions used 8b/10b.
The Link Between Compute Express Link and PCIe
Compute Express Link (CXL), which is built on PCI Express, started with PCIe Gen 5. The CXL Consortium is the keeper of CXL. Its standard releases are independent of PCI-SIG while being based on the PCIe standards.
CXL-attached memory is a key element of the CXL standards. PCIe Gen 6 plus CXL will be of great interest to hyperscalers and data-center designers because of the ability to scale available memory using PCIe connectivity.
Where is PCIe Gen 7?
Now that the PCIe Gen 6 standard is out, work continues with the Gen 7 specification. It looks like it will offer another throughput doubling, but it will retain many of the features of Gen 6, including PAM4 242b/256b signaling. It may show up as early as 2025.
In the meantime, test equipment for Gen 6 is available, while developers push out other hardware in the near future. Backwards compatibility means there will be lots of boards for any new platforms, albeit running less than the maximum speed.
