PCB Layout: The Final Weapon In The Power Designers'Arsenal

May 17, 2007
Should the completion of the circuit design be the end of the road for power designers? After all, once the circuit is verified they have met their design goals, it is time to move on to the next project—right? I say no.

For power designers, power converter design usually ends with the verification of performance in the development lab when the final prototype is tested. From that point on, the task of finalizing this design into a building block for a larger system usually rests with the printed circuit board (PCB) artist. Depending on the final system, dc-dc converters may be left until the end of the design after all the “important” parts of the system have been given the proper attention by assigning the appropriate PCB footprints to them. At the end of this process, which has some justification, whatever PCB space is left gets assigned to the various power converters needed to run the system.

This methodology can and has been made to work in most cases with marginal to acceptable results clearly leading to a working system. But does this approach deliver the best performance? Should the completion of the circuit design be the end of the road for power designers? After all, once the circuit is verified they have met their design goals, it is time to move on to the next project—right? I say no. Don’t walk away from the project until the same attention to detail and optimization given to the circuit design has also been given to the PCB layout.

The PCB layout of a power converter may be looked at as the environment in which the converter thrives or struggles. There are several reasons why this is so. Obviously, the layout must include acceptable trace widths for different current levels. It must also account for the proximity effects of traces and ground planes carrying switching currents to sensitive components like error amplifiers. But the PCB design should also consider less obvious factors such as the parasitic inductance and resistance that the PCB traces introduce to the final circuit.

A general rule that most experienced designers embrace is that the design can only be released after testing and/or simulation of the design at corner values of the components. This step guarantees the design’s performance at all combinations of tolerances likely to be encountered in mass production.

However, parasitic resistances may degrade the converter efficiency by as much as 1% to 3% causing extra heating and shorter battery life in portable designs. This degradation will be discovered only if you look carefully at the PCB traces carrying high switching and dc currents and do some calculation of the parasitic resistance of these traces. Or, if you don’t want to do calculations, the impact of parasitics can be determined by building different versions of the PCB, though that may be impossible given tight budgets and timelines.

Another consideration concerning parasitic resistance is that the higher the frequency of the switched current, the higher the resistance. If we take into consideration switching frequencies of say 1 MHz, this means that the current’s fundamental frequency is 1 MHz, while the rest of the harmonics are at multiples of this frequency. When the duty cycle is low, these harmonics can extend into hundreds of megahertz and each harmonic has its respective parasitic resistance.

Parasitic inductance is the twin of parasitic resistance when considering the influence of the layout on the performance of a given power converter and the entire system. The effects of parasitic inductance range from increases in EMI to excessive losses caused by shoot through in MOSFETs to catastrophic failure of the power switches. The last problem could result from inductance-induced ringing that causes the switches to exceed their maximum rating.

In this last case, particularly with mass produced designs, if the parasitic inductance cannot be reduced to an obviously safe level, I would recommend using Extreme Value Analysis. This methodology can verify that, under no combination of tolerances, will the switches fail.

The dependence of parasitic inductance on frequency is the opposite of parasitic resistance (i.e. the inductance decreases when the frequency is increased.) Several physics-based, finite-element software packages now available in the market can help with these calculations. Then too, there are the old reliable simple formulas that can give you a reasonable estimate of the size of the problem—or lack thereof.

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