Until recently, security implementation in software has been virtually the only option available to design teams, as specific hardware implementations haven’t been readily available on the open market. In addition, many design teams believed they had processing power to spare. The excess power remaining on an embedded processor has been allocated to handle algorithms, including common encryption or decryption routines.
But this is changing with the introduction of security IP. Now, design teams have an alternative approach and can assess chip cost, implementation time, and the overall chip performance tradeoffs of software and hardware implementations.
A simple test case shows how the impact of a hardware implementation can be assessed, looking at the impact of including a 3DES security IP core on a 1 million-gate system-on-a-chip (SoC) implemented in TSMC’s 130-nm Generic process. The standard cell library used is ARM’s free Sage-X library. Adding a soft IP core with this 3DES functionality, which can be implemented in as little as 10,000 gates according to various security IP vendors, yields only a minor die size increase of 0.06 mm2 for less than a 0.2-cent increase in final chip cost.
The potential for significant reduction on embedded processor load, along with a faster implementation, can enhance overall chip performance. Depending upon chip application, price sensitivity, and the importance of the specific security functionality, the minor cost increase could be well worth reducing processor load.
This type of early hardware versus software analysis is best completed at the earliest phase of the design flow. Automated estimation systems can help designers quantify the technical and economic tradeoffs by showing the size, power, and cost advantages or disadvantages of various implementations. The key is to perform the analysis early, when the design team benefits most from looking at the tradeoffs and exploring what options are available to them.
With numerous options now available, successfully navigating the solution space for next-generation designs isn’t only important. It also could mean the difference between the success or failure of the chip.
