Today's FPGAs offer densities of 10 million gates and clock speeds of 400 MHz. Thus, ASIC design starts are trending down while FPGA design starts are on the rise. What's missing is an EDA tool flow for FPGAs that brings some of the advantages of ASIC-style hierarchical methodologies. The braintrust at EDA startup Hier Design Inc., Santa Clara, Calif., thinks it has the answer—adapting silicon virtual prototyping (SVP) technology from ASIC flows for use with FPGAs.
"FPGA design flows have suffered from being flat rather than hierarchical," says Jackson Kreiter, Hier Design's CEO and chairman. "Synthesis runtimes on a 6 to 8 million-gate FPGA are over 24 hours. In a flat flow, you have to resynthesize the entire FPGA if you make a change to one block in the design," said Kreiter.
Hier's block-based, scalable approach sidesteps the problems that stem from a flat approach to FPGA design by inserting hierarchical design planning and logic optimization and placement before routing. Together, these steps make up an SVP capability bolstered by an ongoing financial and technical relationship with Xilinx. Xilinx has cooperated fully in giving Hier Design's tools visibility into their silicon's routing facilities.
Today's FPGA flows involve synthesis tools taking register transfer level to gate level, which is then optimized in physical synthesis. The physical synthesis step involves unmapping the design and revisiting physical placement, obviating much of the optimization. Hier Design's approach will much more closely link design floorplanning and physical synthesis, doing away with interim optimization. Time-to-market promises to improve.
Hier Design intends to introduce its first products in July. They're in the hands of several beta customers now and, according to Kreiter, they've been achieving good results with the tools. They run on Windows, Linux, and Sun Solaris Unix-based workstations.
Hier Design Inc.
www.hierdesign.com
