What you’ll learn:
- The state of RISC-V, including new RISC-V announcements.
- A look at some good video presentations at the 2024 RISC-V Summit.
- RISC-V trends in 2025.
I didn't make it to the RISC-V Summit this year. Luckily, though, they posted most of their keynotes and sessions on their YouTube channel. I selected a few of the videos that stood out for me, which you can watch below.
RISC-V continues to gain momentum with RISC-V IP providers like Andes Technology, Codasip, and SiFive. The availability of RISC-V chips also continues to grow with major suppliers like Microchip Technology and its 64-bit multicore PIC64GX and PIC64HX series on the horizon for 2025. Also in the mix are the currently available PolarFire FPGA SoCs used in platforms like BeagleBoard.com's BeagleV-Fire board.
Scroll down or jump to one of my selections to watch the videos.
- Accelerating AI LLM Models Using RISC-V P-Extensions
- Lessons Learned in Using RISC-V for Generative AI and Where We Can Go from Here
- The Future of Mission Critical Edge Compute Is RISC-V
- Keynote Panel: The Future of AI and Security
- Berberis: Dynamic Binary Translation from RISC-V to X86_64 on Android
Read More About RISC-V
Select Videos from 2024 RISC-V Summit
Accelerating AI LLM Model Using RISC-V P-Extensions
Andes Technology's Yueh-Feng Lee presented LLM Inference on RISC-V Embedded CPUs. This presentation highlights the capabilities of the RISC-V P-extensions for packed SIMD instructions and how they can be used to accelerate artificial-intelligence (AI) large language models (LLMs).
There's a mention of the company's QiLai SoC, which is being developed in conjuction with DeepComputing for an AI-accelerated PC. DeepComputing's DC-ROMA RISC-V Laptop II already uses Spacemit's Ky Stone K1 RISC-V chip.
Lessons Learned in Using RISC-V for Generative AI and Where We Can Go from Here
The Lessons Learned in Using RISC-V for Generative AI and Where We Can Go from Here session was another at the summit that focused on enhancing generative AI.
Esperanto Technologies' Jayesh Iyer and Josep M. Perez delve into the challenges and solutions that were encountered while developing the company's RISC-V AI-accelerated solution. Esperanto's low-power ET-Minion cores in the ET-SoC-1 and ET-SoC-2 were the result.
The Future of Mission Critical Edge Compute Is RISC-V
As mentioned earlier, Microchip is well ensconced with RISC-V. David Levy, Senior Product Marketing Manager at Microchip, gave the The Future of Mission Critical Edge Compute Is RISC-V presentation. This highlights the company's efforts in providing solutions for rugged and mission-critical systems from industrial to military and avionic applications. David touches on the security aspects, including the WorldGuard Partitioning support.
Keynote Panel: The Future of AI and Security
The Keynote Panel: The Future of AI and Security takes a look at the trends in RISC-V and the industry in general. Security has finally made it as a primary topic of discussion with technologies like Rust and CVEs cropping up. Mix that with artificial intelligence and you have the hot topics for the year. There are a half-dozen keynotes and panel discussions from the summit, so check those out as well.
Berberis: Dynamic Binary Translation from RISC-V to X86_64 on Android
The session presented by Google's Lev Rumyantsev and Jeremiah Griffin on Berberis: Dynamic Binary Translation from RISC-V to X86_64 on Android stood out to me because of its title and purpose. Berberis is a Google project that turns RISC-V machine code into x86_64 machine code.
Why you might ask?
Well, cross-development is its primary use. It enables an Android system to run on an x86_64-based PC or server to host native RISC-V applications. In general, the end target platform will likely be a RISC-V-based SoC running Android.
