Smart Peripherals Make Low-Power IoT Possible

The “smart peripheral” approach has many variants with different names, but the general idea is the same. For example, Renesas' RL78 has a “snooze mode” where the analog-to-digital converter (ADC) operates while the processor is asleep. An I²C slave or CAN controller can watch for an address before it captures incoming data and then wakes up the CPU.

In a sense, Cypress Semiconductor’s PSoC flexible family was out in front with configurable digital and analog peripherals. Part of the configuration is the ability to link peripherals together, so an ADC result could be dropped into a serial port to be sent to another device without the CPU being involved. The PSoC configurability is short of what an FPGA can do, but PSoC is significantly easier to configure. The company’s latest PSoC 4 BLE (Bluetooth Low Energy) can run the BLE radio while the CPU is asleep.

Microchip’s Configurable Logic Cell (CLC) highlights the more conventional approach to configurable  peripherals (see "Microcontroller Incorporates Programmable Logic"). A microcontroller may have one or more CLC blocks. Each block has a selectable set of inputs and outputs with limited logic capability so the output of one peripheral can be fed to another. As with the PSoC, linked peripherals can often handle simple algorithms faster than the CPU can programmatically.

STMicroelectronics' STM32 has “autonomous peripherals” that use a “peripheral interconnect matrix” to link peripherals together. Timers, DMAs, ADCs, and DACs can be linked together.

The trend towards more functionality and complexity is highlighted by Microchip’s PIC16F18877 family (see "More Intelligent Signal Processing Targets IoT"). It has a 10- ADC tied to a computational unit that can do accumulation and averaging. It can even do low-pass filter calculations in hardware. The CPU can sleep until a filtered result exceeds programmed limits.

Intelligent hardware is useful, but taking advantage of it is more than just programming the peripherals. Advanced power trace tools like Silicon Labs’ energyAware Profiler (see figure) typically track power usage, as well as active and sleeping device status. This information is more complex because the CPU and peripherals are often operating independently, including their individual power modes. Likewise, different devices need different amounts of power based on the work they are doing.

Part of the challenge for developers is understanding the ways in which different power modes interact with the CPU and peripherals as well as the power cost of using various configurations. The start-up time for the CPU from different modes will be an additional factor.

Even volatile memory comes into play, with some microcontrollers being able to preserve segments of memory while in various sleep modes. Of course, some microcontrollers—like Texas Instrument’s MSP-430—only contain FRAM that is a non-volatile memory, so it is not necessary to be as selective about what data to save between power modes (see "Q&A: TI’s Will Cooper Talks FRAM Memories").

Intelligent peripherals, distributed power management, and energy trace tools are here to stay. Developers can often get better battery life that is an order of magnitude or more of that available with basic CPU sleep modeF over the life of a product for many applications (and not just IoT applications). Doing so requires some research, because microcontroller and peripheral solutions that have this type of facility vary widely in functionality. Some combinations may be more suitable to an application than others.