SiTime's integrated Super-TCXO optimizes RF and synchronization performance, offering up to 30X higher reliability, with up to 20X better environmental resilience in wireless ...
At DAC, Arteris featured its system IP, which includes its network-on-chip interconnect IP and system-on-chip integration automation software to help boost product performance...
Cadence's Joules RTL Design Studio delivers up to 5X faster register-transfer-level convergence and up to 25% improved QoR through fast, accurate, and early physical insight and...
Established as the leading event for the design, engineering, and design automation community, the Design Automation Conference (DAC) highlights the latest developments in the...
More content from Design Automation Conference 2023
The test and analysis GUI from OPENEDGES, code-named PHY Vision, serves as a comprehensive cockpit for visualizing and optimizing the performance of the DDR PHY.
The company's JSPICE software, used for 25 years in-house to make its own PLL and DLL IP, is now available through a beta test in advance of a commercial release.