Graphene-Based Interconnects Could Improve Density of Digital, Analog, and Power ICs

What you’ll learn:

• A new process for creating interconnects on ICs using high-conductivity 2D graphene films could enable production of smaller, faster, cooler-running devices than those using today’s copper technologies.
• The technique, compatible with existing IC fabrication processes, can deposit multiple layers of 2D graphene using fewer process steps.

Destination 2D successfully achieved wafer-scale synthesis of high-quality two-dimensional graphene lattices, suitable for interconnects, using temperatures that fall within the process conditions used to fabricate standard CMOS devices.

The process, known as CoolC GT300, enables the formation of multiple layers of 2D graphene films on semiconductor products. It has the potential to significantly cut resistive losses occurring within devices’ interconnect layers while also producing much less capacitive loading and crosstalk than a conventional copper interconnect network. 

CoolC GT300 can form 2D graphene lattices on wafer-scale dielectric substrates at temperatures significantly below the thermal budgets to fabricate standard CMOS devices, as well as those used for gallium-nitride (GaN) and silicon-carbide (SiC) products. The first step is to deposit a sacrificial metal layer directly on a standard CMOS wafer and then diffuse the carbon through the layer to form a 2D graphene matrix.

The process can be repeated to form multiple layers of graphene, with dopants introduced between layers (using a low-temperature thermal diffusion process (250 to 350°C)), to enhance carrier density that increases their conductivity by up to 100X of an equivalent copper trace. This could enable a 2X to 3X increase in logic density when employing present process geometries.

Improved conductivity also has the potential to eliminate life-limiting problems due to electron migration that arise in VLSI devices using copper-based interconnects as their process geometries approach 15 µm. Moreover, high-power devices are expected to benefit from lower losses and more compact geometries made possible by CoolC GT300. 

In addition to producing films with extremely consistent electrical and mechanical characteristics, CoolC GT300 avoids the warping and cracking issues that have plagued previous graphene interconnect processes.

Destination 2D said that the technology, which has been successfully used in coupon-scale demonstrations on 300-mm wafers, can reduce the number of process steps and eliminate up to $12M worth of process equipment per process layer in CMOS manufacturing applications. The company also noted that CoolC GT300 technology can be applied to GaN and SiC processes.