Arm

The MIPS P8700 RISC-V core, which implements a RISC-V ISA, aims at ASIL B and ISO 26262 functional safety.

Arm Cortex-M0+—a reliable architecture with low-power needs—provides 32-bit capabilities in a compact and efficient form factor.

The combination of X925, A725, and A520 cores, Arm’s most powerful mobile CPU cluster for AI to date, brings 46% better performance than CPU clusters based on the Cortex-X4 released...

Microcontrollers and other small systems are the latest to embrace AI, and hardware vendors are leading the charge with fresh innovations.

The Cortex-M52 forms a family with the M85 and M55, all of which are based on Arm’s Helium technology.

The CSS significantly reduces SoC engineering overhead for faster time-to-market.