Designing with Chiplets

Mixing dies, interposers, and designs to fabricate new solutions.

Intel paired one of its CPUs with an optical compute interconnect (OCI) chiplet.

Siemens’ Xpedition Substrate Integrator provides co-design prototyping and planning of 2.5/3D chips.

Cadence's UCIe demo presents key features and interoperability support, and also discusses the future of chiplet technology in high-performance SoCs.

Discover how the Universal Memory Interface tackles substrate- and die-level real-estate challenges in chiplet-based design, unlocking performance and scalability.

The company’s next-gen AI silicon adds more accelerator cores, faster networking, and extra high-bandwidth memory.

Learn more about Pike Creek and its potential implications as the first test chip featuring chiplets linked by the UCIe standard.

This superpanel explores the role of chiplets in advancing ever-expanding generative AI technology.

When it comes to chiplets, it’s all about packaging technology.

Wrapping up the 2024 Chiplet Summit, this panel session discussed the huge advantages and persistent challenges presented by chiplets.

Abhijeet Chakraborty, Vice President of Engineering at Synopsys, in his keynote at the 2024 Chiplet Summit, said that last year was an inflection point for multi-die systems.

Explore Keysight’s Chiplet PHY Designer tool and the game-changing UCIe standard in chip design.

The Chiplet Summit is coming up at the beginning of February. I hope to meet up with you there.

Intel’s latest data-center CPU is a prelude to the process and packaging innovations it has in store for 2024.

With the right investments, chiplets can help solve long-standing industry challenges such as increasing costs and supply disruptions, resulting in a world where devices are more...

Jim Handy’s crystal ball reveals trends about many topics, ranging from memory chips to generative AI.

Intel is looking to use glass, which has strong thermal and mechanical characteristics, as a substrate for chiplets.

Explore the main driving forces behind today’s multi-die systems, how they’re becoming the choice system architecture, and how they’re catalyzing the next wave of semiconductor...

The Versal Premium adaptive System-on-Chip (SoC) targets EDA simulation and verification applications.

Intel’s Agilex 7 with R-Tile support works with PCIe 5.0 and CXL.

AMD will utilize a range of 2.5D and 3D chiplets to integrate systems that will include the company's FPGA technology.

The recently announced Universal Chiplet Interconnect Express standard, based on PCIe and CXL, will help simplify chip design.

Chiplets – Electronic Design Automation Insights

zGlue’s ChipBuilder Pro lets designers create chips using its 2.5D chiplet Smart Fabric.

TSMC Works With Arm to Chart Future of Chiplets

Intel Adds New Technology to Advanced Packaging Arsenal

Intel Introduces New Way to Stack Chips on Top of Each Other

This silicon interposer fabric lets developers integrate multiple die into a single, compact chip. It is ideal for compact form factors needed for applications like wearable devices...